noracarmig
72020fc012
Reset complete count global variable on Dma configure
2025-01-26 14:53:10 +00:00
Georges Palauqui
da0f6dbe08
derive defmt::Format on pub struct/enum of stm32::rtc
2025-01-24 11:58:33 +01:00
Dario Nieuwenhuis
4e3d066251
Merge pull request #3779 from algesten/fix/f107-rcc
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Full RCC support for STM32F107
2025-01-24 09:13:45 +00:00
Martin Algesten
4743501172
Move PLL2/3 config to before PLL
2025-01-24 10:06:32 +01:00
Martin Algesten
3ba94c0ab3
Fix init order of set_prediv1src
2025-01-24 09:36:11 +01:00
Martin Algesten
c72d9ec859
Review fixes
2025-01-24 09:16:24 +01:00
nikvoid
afe6b9a192
split PHY constructor to new and new_auto
2025-01-23 13:34:54 +02:00
nikvoid
dff8be9bb6
run rustfmt
2025-01-22 18:11:32 +02:00
nikvoid
83ccbf48d7
remove cortex-m delay
2025-01-22 18:09:25 +02:00
nikvoid
2d7e0b6e0f
use Delay from embassy-time to wait for PHY response
2025-01-22 13:43:45 +02:00
nikvoid
5885369f47
Option to detect Ethernet PHY address automatically
2025-01-22 13:23:29 +02:00
Dario Nieuwenhuis
010d4622f9
Merge pull request #3765 from dimpolo/hertz-display
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stm32: impl Display for time::Hertz
2025-01-22 00:34:40 +01:00
Dario Nieuwenhuis
eda51673f5
Merge pull request #3704 from CNLHC/pwm_support_gp32
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feat: Add 32-bit timer support for waveform function
2025-01-21 22:57:47 +00:00
Dario Nieuwenhuis
5bba87e0c9
Merge pull request #3782 from Andreychik32/main
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stm32/can: fix wrong negation of fdcan set_transmit_pause function parameter
2025-01-21 22:29:57 +00:00
Andrii
08ef834301
fix wrong negation of fdcan set_transmit_pause function parameter
2025-01-17 18:05:50 +02:00
Markus Kasten
5d26bca2e7
stm32/rcc: add HSISYS support for g0
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adds support to divide HSI clock, which allows running in low power mode on HSI
2025-01-17 12:07:43 +01:00
Martin Algesten
9a159a8db0
Full RCC support for STM32F107
2025-01-16 15:31:41 +01:00
dimi
1c9fa80492
stm32: impl Display for time::Hertz
2025-01-13 11:30:49 +01:00
Volkalex28
fb1368d9c8
Fix unsupported trace! call for EndpointAddress
2025-01-09 11:02:47 +02:00
Matt Rodgers
844d3b38de
stm32: flash: fix flash erase on stm32f3xx series
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STM32F3xx series also needs a wait of at least one clock cycle before
reading the BSY bit during a flash erase - previously this was only
applied to STM32F1xx series.
2025-01-08 10:11:25 +00:00
Dario Nieuwenhuis
06869e2e85
Merge pull request #3725 from CNLHC/qspi_mmap
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feat: mmap mode for qspi and example
2025-01-07 22:36:01 +01:00
Dario Nieuwenhuis
2a06eb2459
Merge pull request #3667 from williams-one/stm32u5-add-hspi-support
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STM32U5: add HSPI support
2025-01-07 21:15:54 +00:00
Dario Nieuwenhuis
90cb610ef7
Merge pull request #3716 from elagil/fix_stm32f4_i2s_clocks
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Fix STM32F4 I2S clock calculations
2025-01-07 22:06:20 +01:00
Dario Nieuwenhuis
d08116da49
Fix typo.
2025-01-07 22:00:41 +01:00
William Spinelli
19efea195d
stm32u5: Add support for HSPI peripheral
2025-01-07 21:55:08 +01:00
Liu Hancheng
09cc9c65c9
feat: mmap mode for qspi and example
2025-01-07 21:47:27 +01:00
Dario Nieuwenhuis
7c3099b9e2
Merge pull request #3724 from CNLHC/qspi_waiting_condition
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FIX: QSPI synchronous read operation hangs when FIFO is not full
2025-01-07 20:38:51 +00:00
Ivan Li
a3c1b18b02
feat: calibrating Differential ADC for G4
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Signed-off-by: Ivan Li <ivanli2048@gmail.com>
2025-01-07 21:28:55 +08:00
Tamme Dittrich
7ac2a4f674
Allow split CAN Rx to modify the filters
2025-01-07 10:11:53 +01:00
Dario Nieuwenhuis
7f05c1e439
Update stm32-metapac.
2025-01-06 15:40:05 +01:00
Liu Hancheng
cfd5c92375
fix typo
2025-01-05 20:10:45 +08:00
Liu Hancheng
e15e30add2
fix: fix qspi waiting condition
2025-01-05 20:00:15 +08:00
Liu Hancheng
4ad3b66e45
refactor: update write DMA transfer function to use separate memory word type
2025-01-05 10:25:10 +08:00
Gabriel Smith
4c8ee8786f
stm32: Implement reads of DTS peripheral
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Only PCLK-driven operation is supported.
2025-01-04 13:56:41 -05:00
Liu Hancheng
50e98a9a58
refactor: update DMA transfer functions to support separate memory and peripheral word types
2025-01-04 22:10:47 +08:00
Liu Hancheng
03dd50316c
refactor: simplify timer bits handling
2025-01-04 21:38:22 +08:00
Liu Hancheng
7d74d15b18
refactor: update DMA pointer types for cryp and hash modules
2025-01-04 21:10:32 +08:00
Liu Hancheng
ff526e1604
refactor: update DMA transfer functions to use separate memory and peripheral sizes
2025-01-04 20:16:34 +08:00
elagil
d672dc8626
fix: unneeded mutability
2025-01-03 23:40:09 +01:00
elagil
a901fe2f02
fix: unused import
2025-01-03 23:03:42 +01:00
elagil
24fdd25e51
fix: configuration logic
2025-01-03 23:01:46 +01:00
elagil
cf606a161f
fix: STM32F4 I2S clock calculations
2025-01-03 22:57:31 +01:00
elagil
eba8089601
chore: fix build
2025-01-03 18:18:00 +01:00
elagil
d9ef2c94d7
chore: clean up stm32h5 ucpd
2025-01-03 17:54:59 +01:00
chanterheld
d368760424
fix stmd g0/g4 formatting and bker bit access
2025-01-02 21:14:06 +01:00
chanterheld
c706e3797a
fix g0 wait_busy
2025-01-02 20:20:38 +01:00
chanterheld
f1ffbf2f7e
embassy-stm32. support g0 second flash bank
2025-01-02 20:05:01 +01:00
Ian McKernan
28d58578d6
remove trailing space from comment
2025-01-01 21:59:29 -08:00
Ian McKernan
9e9fa1cbef
added fix for https://github.com/embassy-rs/embassy/issues/2496 in the v1 driver
2025-01-01 21:47:44 -08:00
Liu Hancheng
90b4164426
dev: change name to bits
2025-01-02 12:51:47 +08:00
