Merge pull request #3716 from elagil/fix_stm32f4_i2s_clocks
Fix STM32F4 I2S clock calculations
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commit
90cb610ef7
@ -714,6 +714,16 @@ fn main() {
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// Generate RCC
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clock_gen.clock_names.insert("sys".to_string());
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clock_gen.clock_names.insert("rtc".to_string());
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// STM32F4 SPI in I2S mode receives a clock input from the dedicated I2S PLL.
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// For this, there is an additional clock MUX, which is not present in other
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// peripherals and does not fit the current RCC structure of stm32-data.
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if chip_name.starts_with("stm32f4") && !chip_name.starts_with("stm32f410") {
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clock_gen.clock_names.insert("plli2s1_p".to_string());
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clock_gen.clock_names.insert("plli2s1_q".to_string());
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clock_gen.clock_names.insert("plli2s1_r".to_string());
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}
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let clock_idents: Vec<_> = clock_gen.clock_names.iter().map(|n| format_ident!("{}", n)).collect();
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g.extend(quote! {
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#[derive(Clone, Copy, Debug)]
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@ -458,7 +458,7 @@ impl<'d, W: Word> I2S<'d, W> {
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/// Write data directly to the raw I2S ringbuffer.
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/// This can be used to fill the buffer before starting the DMA transfer.
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pub async fn write_immediate(&mut self, data: &mut [W]) -> Result<(usize, usize), Error> {
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pub async fn write_immediate(&mut self, data: &[W]) -> Result<(usize, usize), Error> {
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match &mut self.tx_ring_buffer {
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Some(ring) => Ok(ring.write_immediate(data)?),
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_ => return Err(Error::NotATransmitter),
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@ -491,10 +491,9 @@ impl<'d, W: Word> I2S<'d, W> {
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let regs = T::info().regs;
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// TODO move i2s to the new mux infra.
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//#[cfg(all(rcc_f4, not(stm32f410)))]
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//let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
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//#[cfg(stm32f410)]
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#[cfg(all(rcc_f4, not(stm32f410)))]
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let pclk = unsafe { crate::rcc::get_freqs() }.plli2s1_r.to_hertz().unwrap();
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#[cfg(not(all(rcc_f4, not(stm32f410))))]
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let pclk = T::frequency();
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let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);
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