165 lines
4.6 KiB
Markdown
165 lines
4.6 KiB
Markdown
---
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path: /elektro/hr/rts10/
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tags: kladjes, elektro, elektro/hr, elektro/hr/rts10
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auther:
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- Finley van Reenen (0964590@hr.nl)
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auther_short: "E.L.F. van Reenen"
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---
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# Report Week 1.2
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## volatile
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`volatile` is a keyword in c to specify to the comiler it soult not optimize the variable away. This can be usfull for debugging perpeses, if a it is used somewhere the compiler does not reconize or (for example hardwere registers). I learnd this form colleagues on my internship at Erisk.
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## assignment 2.2
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> will in line 14 and 21^[line numerbers differ from the assignment, becouse change longer lines te prevent linewrapping] to alternate the green and red with oragne and blue.
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The pinout is as followed
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orange: port D bit 13
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green: port D bit 12
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red: port D bit 14
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blue: port D bit 15
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Bit 12 and 14 sould start different as bit 13 and 15. Then invert all four bits every loop to achees the assignment.
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I found the defines in the sourcefile where the _modder_ defines are defined.
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```c-like=
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#include <stdint.h>
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#include <stm32f4xx.h>
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int main(void)
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{
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// GPIO Port D Clock Enable
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RCC->AHB1ENR = RCC_AHB1ENR_GPIODEN;
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// GPIO Port D Pin 15 down to 12 Push/Pull Output
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GPIOD->MODER = GPIO_MODER_MODER12_0
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| GPIO_MODER_MODER13_0
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| GPIO_MODER_MODER14_0
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| GPIO_MODER_MODER15_0;
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// Set green and red LEDs
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GPIOD->ODR = GPIO_ODR_OD12 | GPIO_ODR_OD14;
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// Do forever:
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while (1)
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{
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// Wait a moment
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for (volatile int32_t i = 0; i < 1000000; i++);
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// Flip all LEDs
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GPIOD->ODR ^= GPIO_ODR_OD12
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| GPIO_ODR_OD13
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| GPIO_ODR_OD14
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| GPIO_ODR_OD15;
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}
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}
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```
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> How is the assambly generated for line 9 compeard to the magic value `0x55000000`
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The compiler regonizes that it can calculate the or opperations at compile time becouse it only used compile time defines as inputs. This reults in the foloing line of assambly.
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```asm
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mov.w r2, #1426063360 @ 0x55000000
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```
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## assignment 2.3
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skiped
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## assignment 2.4
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skiped
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## assignment 2.5
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> Copy the project from assignment 2.2 and update the clock to use the $8 MHz$ external cristal (HSE).
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I added line 6 throw 15, the rest is uncheached.
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```c-like=
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#include <stdint.h>
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#include <stm32f4xx.h>
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int main(void)
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{
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// Enable HSE
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RCC->CR |= RCC_CR_HSEON;
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// Wait until HSE is stable
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while ((RCC->CR & RCC_CR_HSERDY) == 0);
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// Select HSE as the system clock
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RCC->CFGR |= RCC_CFGR_SW_HSE;
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// Wait until HSE used as the system clock
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while ((RCC->CFGR & RCC_CFGR_SWS_HSE ) == 0);
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// Disable HSI
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RCC->CR &= ~RCC_CR_HSION;
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// GPIO Port D Clock Enable
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RCC->AHB1ENR = RCC_AHB1ENR_GPIODEN;
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// GPIO Port D Pin 15 down to 12 Push/Pull Output
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GPIOD->MODER = GPIO_MODER_MODER12_0
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| GPIO_MODER_MODER13_0
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| GPIO_MODER_MODER14_0
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| GPIO_MODER_MODER15_0;
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// Set green and red LEDs
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GPIOD->ODR = GPIO_ODR_OD12 | GPIO_ODR_OD14;
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// Do forever:
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while (1)
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{
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// Wait a moment
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for (volatile int32_t i = 0; i < 1000000; i++);
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// Flip all LEDs
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GPIOD->ODR ^= GPIO_ODR_OD12
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| GPIO_ODR_OD13
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| GPIO_ODR_OD14
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| GPIO_ODR_OD15;
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}
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}
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```
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I mesured the toggle time to be around 1.5 seconsds. This is what is expected.
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> Make use of the PLL to acheef a CPU clock of $100MHz$.
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First the power modules needs to be configured to allow for the hige clockspeed.
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```c-like
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// enable power control
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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// set voltage to support 100 MHz
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PWR->CR |= PWR_CR_VOS_0 | PWR_CR_VOS_1;
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```
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Now the flash latancy is set. The powersupply on the board is $3V$. This means there sould be 3 wait states.
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```c-like
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// set flash latency to support 100 MHz
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FLASH->ACR |= FLASH_ACR_LATENCY_3WS;
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// Wait until the wait states are used
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while ((FLASH->ACR & /* ... */ ) == 0);
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```
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Finaly we configur the PLL itself.
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$$
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f_{(VCO\ clock)} = f_{(PLL\ clock\ input)} \cdot (\frac{PLLN}{PLLM})
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$$
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$$
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f_{(PLL\ general\ clock\ output)} = \frac{f_{(VCO\ clock)}}{PLLP}
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$$
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$f_{(PLL\ clock\ input)} = 8 MHz$
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$f_{(PLL\ general\ clock\ output)} = 100 MHz$
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$100 MHz \leq f_{(VCO\ clock)} \leq 432 MHz$
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$PLLP \rightarrow \{2, 4, 6, 8\}$
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$50 \leq PLLN \leq 432$
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$2 \leq PLLM \leq 63$
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Becouse of the liminitan of $PLLP$, $f_{(VCO\ clock)}$ can only be 200 or 400 MHz to acheve the correct $f_{(PLL\ general\ clock\ output)}$.
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...
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