517 lines
16 KiB
Rust
517 lines
16 KiB
Rust
pub use crate::pac::pwr::vals::Vos as VoltageScale;
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#[cfg(all(peri_usb_otg_hs))]
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pub use crate::pac::rcc::vals::Otghssel;
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Msirange, Msirange as MSIRange, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
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Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
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};
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use crate::pac::rcc::vals::{Hseext, Msirgsel, Pllmboost, Pllrge};
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#[cfg(all(peri_usb_otg_hs))]
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pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::LSI_FREQ;
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
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Bypass,
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/// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
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BypassDigital,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// The clock source for the PLL.
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pub source: PllSource,
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/// The PLL pre-divider.
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///
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/// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
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pub prediv: PllPreDiv,
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/// The PLL multiplier.
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///
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/// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
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/// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
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pub mul: PllMul,
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/// The divider for the P output.
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///
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/// The P output is one of several options
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/// that can be used to feed the SAI/MDF/ADF Clock mux's.
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pub divp: Option<PllDiv>,
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/// The divider for the Q output.
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///
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/// The Q ouput is one of severals options that can be used to feed the 48MHz clocks
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/// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's.
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pub divq: Option<PllDiv>,
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/// The divider for the R output.
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///
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/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
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/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
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/// `Config { voltage_range }`.
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pub divr: Option<PllDiv>,
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}
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#[derive(Clone, Copy)]
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pub struct Config {
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// base clock sources
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pub msis: Option<MSIRange>,
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pub msik: Option<MSIRange>,
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pub hsi: bool,
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pub hse: Option<Hse>,
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pub hsi48: Option<super::Hsi48Config>,
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// pll
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pub pll1: Option<Pll>,
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pub pll2: Option<Pll>,
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pub pll3: Option<Pll>,
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// sysclk, buses.
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pub sys: Sysclk,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub apb3_pre: APBPrescaler,
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/// The voltage range influences the maximum clock frequencies for different parts of the
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/// device. In particular, system clocks exceeding 110 MHz require `RANGE1`, and system clocks
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/// exceeding 55 MHz require at least `RANGE2`.
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///
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/// See RM0456 § 10.5.4 for a general overview and § 11.4.10 for clock source frequency limits.
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pub voltage_range: VoltageScale,
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pub ls: super::LsConfig,
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/// Per-peripheral kernel clock selection muxes
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pub mux: super::mux::ClockMux,
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}
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impl Config {
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pub const fn new() -> Self {
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Self {
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msis: Some(Msirange::RANGE_4MHZ),
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msik: Some(Msirange::RANGE_4MHZ),
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hse: None,
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hsi: false,
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hsi48: Some(crate::rcc::Hsi48Config::new()),
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pll1: None,
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pll2: None,
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pll3: None,
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sys: Sysclk::MSIS,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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apb3_pre: APBPrescaler::DIV1,
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voltage_range: VoltageScale::RANGE1,
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ls: crate::rcc::LsConfig::new(),
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mux: super::mux::ClockMux::default(),
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}
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}
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}
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impl Default for Config {
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fn default() -> Self {
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Self::new()
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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// Set the requested power mode
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PWR.vosr().modify(|w| w.set_vos(config.voltage_range));
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while !PWR.vosr().read().vosrdy() {}
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let msis = config.msis.map(|range| {
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// Check MSI output per RM0456 § 11.4.10
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match config.voltage_range {
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VoltageScale::RANGE4 => {
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assert!(msirange_to_hertz(range).0 <= 24_000_000);
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}
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_ => {}
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}
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// RM0456 § 11.8.2: spin until MSIS is off or MSIS is ready before setting its range
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loop {
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let cr = RCC.cr().read();
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if cr.msison() == false || cr.msisrdy() == true {
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break;
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}
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}
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RCC.icscr1().modify(|w| {
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w.set_msisrange(range);
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w.set_msirgsel(Msirgsel::ICSCR1);
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});
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RCC.cr().write(|w| {
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w.set_msipllen(false);
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w.set_msison(true);
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});
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while !RCC.cr().read().msisrdy() {}
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msirange_to_hertz(range)
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});
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let msik = config.msik.map(|range| {
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// Check MSI output per RM0456 § 11.4.10
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match config.voltage_range {
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VoltageScale::RANGE4 => {
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assert!(msirange_to_hertz(range).0 <= 24_000_000);
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}
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_ => {}
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}
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// RM0456 § 11.8.2: spin until MSIS is off or MSIS is ready before setting its range
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loop {
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let cr = RCC.cr().read();
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if cr.msikon() == false || cr.msikrdy() == true {
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break;
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}
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}
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RCC.icscr1().modify(|w| {
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w.set_msikrange(range);
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w.set_msirgsel(Msirgsel::ICSCR1);
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});
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RCC.cr().write(|w| {
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w.set_msikon(true);
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});
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while !RCC.cr().read().msikrdy() {}
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msirange_to_hertz(range)
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});
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let hsi = config.hsi.then(|| {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ
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});
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let hse = config.hse.map(|hse| {
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// Check frequency limits per RM456 § 11.4.10
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match config.voltage_range {
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VoltageScale::RANGE1 | VoltageScale::RANGE2 | VoltageScale::RANGE3 => {
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assert!(hse.freq.0 <= 50_000_000);
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}
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VoltageScale::RANGE4 => {
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assert!(hse.freq.0 <= 25_000_000);
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}
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}
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// Enable HSE, and wait for it to stabilize
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RCC.cr().write(|w| {
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w.set_hseon(true);
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w.set_hsebyp(hse.mode != HseMode::Oscillator);
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w.set_hseext(match hse.mode {
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HseMode::Oscillator | HseMode::Bypass => Hseext::ANALOG,
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HseMode::BypassDigital => Hseext::DIGITAL,
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});
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});
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while !RCC.cr().read().hserdy() {}
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hse.freq
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});
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let hsi48 = config.hsi48.map(super::init_hsi48);
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let pll_input = PllInput { hse, hsi, msi: msis };
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let pll1 = init_pll(PllInstance::Pll1, config.pll1, &pll_input, config.voltage_range);
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let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range);
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let pll3 = init_pll(PllInstance::Pll3, config.pll3, &pll_input, config.voltage_range);
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let sys_clk = match config.sys {
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Sysclk::HSE => hse.unwrap(),
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Sysclk::HSI => hsi.unwrap(),
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Sysclk::MSIS => msis.unwrap(),
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Sysclk::PLL1_R => pll1.r.unwrap(),
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};
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// Do we need the EPOD booster to reach the target clock speed per § 10.5.4?
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if sys_clk >= Hertz::mhz(55) {
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// Enable the booster
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PWR.vosr().modify(|w| w.set_boosten(true));
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while !PWR.vosr().read().boostrdy() {}
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}
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// The clock source is ready
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// Calculate and set the flash wait states
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let wait_states = match config.voltage_range {
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// VOS 1 range VCORE 1.26V - 1.40V
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VoltageScale::RANGE1 => match sys_clk.0 {
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..=32_000_000 => 0,
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..=64_000_000 => 1,
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..=96_000_000 => 2,
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..=128_000_000 => 3,
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_ => 4,
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},
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// VOS 2 range VCORE 1.15V - 1.26V
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VoltageScale::RANGE2 => match sys_clk.0 {
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..=30_000_000 => 0,
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..=60_000_000 => 1,
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..=90_000_000 => 2,
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_ => 3,
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},
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// VOS 3 range VCORE 1.05V - 1.15V
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VoltageScale::RANGE3 => match sys_clk.0 {
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..=24_000_000 => 0,
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..=48_000_000 => 1,
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_ => 2,
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},
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// VOS 4 range VCORE 0.95V - 1.05V
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VoltageScale::RANGE4 => match sys_clk.0 {
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..=12_000_000 => 0,
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_ => 1,
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},
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};
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FLASH.acr().modify(|w| {
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w.set_latency(wait_states);
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});
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// Switch the system clock source
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RCC.cfgr1().modify(|w| w.set_sw(config.sys));
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while RCC.cfgr1().read().sws() != config.sys {}
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// Configure the bus prescalers
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RCC.cfgr2().modify(|w| {
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w.set_hpre(config.ahb_pre);
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w.set_ppre1(config.apb1_pre);
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w.set_ppre2(config.apb2_pre);
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});
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RCC.cfgr3().modify(|w| {
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w.set_ppre3(config.apb3_pre);
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});
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let hclk = sys_clk / config.ahb_pre;
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let hclk_max = match config.voltage_range {
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VoltageScale::RANGE1 => Hertz::mhz(160),
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VoltageScale::RANGE2 => Hertz::mhz(110),
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VoltageScale::RANGE3 => Hertz::mhz(55),
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VoltageScale::RANGE4 => Hertz::mhz(25),
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};
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assert!(hclk <= hclk_max);
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
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let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
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let (pclk3, _) = super::util::calc_pclk(hclk, config.apb3_pre);
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let rtc = config.ls.init();
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#[cfg(all(stm32u5, peri_usb_otg_hs))]
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let usb_refck = match config.mux.otghssel {
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Otghssel::HSE => hse,
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Otghssel::HSE_DIV_2 => hse.map(|hse_val| hse_val / 2u8),
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Otghssel::PLL1_P => pll1.p,
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Otghssel::PLL1_P_DIV_2 => pll1.p.map(|pll1p_val| pll1p_val / 2u8),
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};
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#[cfg(all(stm32u5, peri_usb_otg_hs))]
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let usb_refck_sel = match usb_refck {
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Some(clk_val) => match clk_val {
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Hertz(16_000_000) => Usbrefcksel::MHZ16,
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Hertz(19_200_000) => Usbrefcksel::MHZ19_2,
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Hertz(20_000_000) => Usbrefcksel::MHZ20,
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Hertz(24_000_000) => Usbrefcksel::MHZ24,
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Hertz(26_000_000) => Usbrefcksel::MHZ26,
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Hertz(32_000_000) => Usbrefcksel::MHZ32,
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_ => panic!("cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
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},
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None => Usbrefcksel::MHZ24,
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};
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#[cfg(all(stm32u5, peri_usb_otg_hs))]
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SYSCFG.otghsphycr().modify(|w| {
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w.set_clksel(usb_refck_sel);
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});
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let lse = config.ls.lse.map(|l| l.frequency);
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let lsi = config.ls.lsi.then_some(LSI_FREQ);
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config.mux.init();
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set_clocks!(
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sys: Some(sys_clk),
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hclk1: Some(hclk),
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hclk2: Some(hclk),
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hclk3: Some(hclk),
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pclk1: Some(pclk1),
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pclk2: Some(pclk2),
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pclk3: Some(pclk3),
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pclk1_tim: Some(pclk1_tim),
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pclk2_tim: Some(pclk2_tim),
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msik: msik,
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hsi48: hsi48,
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rtc: rtc,
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lse: lse,
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lsi: lsi,
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hse: hse,
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hsi: hsi,
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pll1_p: pll1.p,
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pll1_q: pll1.q,
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pll1_r: pll1.r,
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pll2_p: pll2.p,
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pll2_q: pll2.q,
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pll2_r: pll2.r,
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pll3_p: pll3.p,
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pll3_q: pll3.q,
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pll3_r: pll3.r,
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#[cfg(dsihost)]
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dsi_phy: None, // DSI PLL clock not supported, don't call `RccPeripheral::frequency()` in the drivers
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// TODO
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audioclk: None,
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shsi: None,
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);
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}
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fn msirange_to_hertz(range: Msirange) -> Hertz {
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match range {
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Msirange::RANGE_48MHZ => Hertz(48_000_000),
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Msirange::RANGE_24MHZ => Hertz(24_000_000),
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Msirange::RANGE_16MHZ => Hertz(16_000_000),
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Msirange::RANGE_12MHZ => Hertz(12_000_000),
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Msirange::RANGE_4MHZ => Hertz(4_000_000),
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Msirange::RANGE_2MHZ => Hertz(2_000_000),
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Msirange::RANGE_1_33MHZ => Hertz(1_330_000),
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Msirange::RANGE_1MHZ => Hertz(1_000_000),
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Msirange::RANGE_3_072MHZ => Hertz(3_072_000),
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Msirange::RANGE_1_536MHZ => Hertz(1_536_000),
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Msirange::RANGE_1_024MHZ => Hertz(1_024_000),
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Msirange::RANGE_768KHZ => Hertz(768_000),
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Msirange::RANGE_400KHZ => Hertz(400_000),
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Msirange::RANGE_200KHZ => Hertz(200_000),
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Msirange::RANGE_133KHZ => Hertz(133_000),
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Msirange::RANGE_100KHZ => Hertz(100_000),
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}
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}
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pub(super) struct PllInput {
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pub hsi: Option<Hertz>,
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pub hse: Option<Hertz>,
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pub msi: Option<Hertz>,
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}
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#[allow(unused)]
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#[derive(Default)]
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pub(super) struct PllOutput {
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pub p: Option<Hertz>,
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pub q: Option<Hertz>,
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pub r: Option<Hertz>,
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}
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#[derive(PartialEq, Eq, Clone, Copy)]
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enum PllInstance {
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Pll1 = 0,
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Pll2 = 1,
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Pll3 = 2,
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}
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fn pll_enable(instance: PllInstance, enabled: bool) {
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RCC.cr().modify(|w| w.set_pllon(instance as _, enabled));
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while RCC.cr().read().pllrdy(instance as _) != enabled {}
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}
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fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale) -> PllOutput {
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// Disable PLL
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pll_enable(instance, false);
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let Some(pll) = config else { return PllOutput::default() };
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let src_freq = match pll.source {
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PllSource::DISABLE => panic!("must not select PLL source as DISABLE"),
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PllSource::HSE => unwrap!(input.hse),
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PllSource::HSI => unwrap!(input.hsi),
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PllSource::MSIS => unwrap!(input.msi),
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};
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// Calculate the reference clock, which is the source divided by m
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let ref_freq = src_freq / pll.prediv;
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// Check limits per RM0456 § 11.4.6
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assert!(Hertz::mhz(4) <= ref_freq && ref_freq <= Hertz::mhz(16));
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// Check PLL clocks per RM0456 § 11.4.10
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let (vco_min, vco_max, out_max) = match voltage_range {
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VoltageScale::RANGE1 => (Hertz::mhz(128), Hertz::mhz(544), Hertz::mhz(208)),
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VoltageScale::RANGE2 => (Hertz::mhz(128), Hertz::mhz(544), Hertz::mhz(110)),
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VoltageScale::RANGE3 => (Hertz::mhz(128), Hertz::mhz(330), Hertz::mhz(55)),
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VoltageScale::RANGE4 => panic!("PLL is unavailable in voltage range 4"),
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};
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// Calculate the PLL VCO clock
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let vco_freq = ref_freq * pll.mul;
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assert!(vco_freq >= vco_min && vco_freq <= vco_max);
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// Calculate output clocks.
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let p = pll.divp.map(|div| vco_freq / div);
|
||
let q = pll.divq.map(|div| vco_freq / div);
|
||
let r = pll.divr.map(|div| vco_freq / div);
|
||
for freq in [p, q, r] {
|
||
if let Some(freq) = freq {
|
||
assert!(freq <= out_max);
|
||
}
|
||
}
|
||
|
||
let divr = match instance {
|
||
PllInstance::Pll1 => RCC.pll1divr(),
|
||
PllInstance::Pll2 => RCC.pll2divr(),
|
||
PllInstance::Pll3 => RCC.pll3divr(),
|
||
};
|
||
divr.write(|w| {
|
||
w.set_plln(pll.mul);
|
||
w.set_pllp(pll.divp.unwrap_or(PllDiv::DIV1));
|
||
w.set_pllq(pll.divq.unwrap_or(PllDiv::DIV1));
|
||
w.set_pllr(pll.divr.unwrap_or(PllDiv::DIV1));
|
||
});
|
||
|
||
let input_range = match ref_freq.0 {
|
||
..=8_000_000 => Pllrge::FREQ_4TO8MHZ,
|
||
_ => Pllrge::FREQ_8TO16MHZ,
|
||
};
|
||
|
||
macro_rules! write_fields {
|
||
($w:ident) => {
|
||
$w.set_pllpen(pll.divp.is_some());
|
||
$w.set_pllqen(pll.divq.is_some());
|
||
$w.set_pllren(pll.divr.is_some());
|
||
$w.set_pllm(pll.prediv);
|
||
$w.set_pllsrc(pll.source);
|
||
$w.set_pllrge(input_range);
|
||
};
|
||
}
|
||
|
||
match instance {
|
||
PllInstance::Pll1 => RCC.pll1cfgr().write(|w| {
|
||
// § 10.5.4: if we're targeting >= 55 MHz, we must configure PLL1MBOOST to a prescaler
|
||
// value that results in an output between 4 and 16 MHz for the PWR EPOD boost
|
||
if r.unwrap() >= Hertz::mhz(55) {
|
||
// source_clk can be up to 50 MHz, so there's just a few cases:
|
||
let mboost = match src_freq.0 {
|
||
..=16_000_000 => Pllmboost::DIV1, // Bypass, giving EPOD 4-16 MHz
|
||
..=32_000_000 => Pllmboost::DIV2, // Divide by 2, giving EPOD 8-16 MHz
|
||
_ => Pllmboost::DIV4, // Divide by 4, giving EPOD 8-12.5 MHz
|
||
};
|
||
w.set_pllmboost(mboost);
|
||
}
|
||
write_fields!(w);
|
||
}),
|
||
PllInstance::Pll2 => RCC.pll2cfgr().write(|w| {
|
||
write_fields!(w);
|
||
}),
|
||
PllInstance::Pll3 => RCC.pll3cfgr().write(|w| {
|
||
write_fields!(w);
|
||
}),
|
||
}
|
||
|
||
// Enable PLL
|
||
pll_enable(instance, true);
|
||
|
||
PllOutput { p, q, r }
|
||
}
|