45 Commits

Author SHA1 Message Date
ROMemories
da86052586 feat(stm32-u5): provide a const constructor on rcc::Config 2025-05-21 14:19:21 +02:00
Dario Nieuwenhuis
7512c5f14e stm32: update metapac, cleanup clocks a bit. 2025-04-18 20:32:15 +02:00
Steven Friedman
bbf2a641dd
remove Hz from log 2025-04-08 09:36:35 -04:00
Marvin Drees
a0e056a629
Update STM32U5 OTG HS clock handling
Signed-off-by: Marvin Drees <marvin.drees@9elements.com>
2024-12-10 13:10:06 +01:00
Christian Enderle
cf2424f5c2 RCC: add lsi and lse clock frequency for STM32U5 2024-11-07 14:16:10 +01:00
Christian Enderle
7231032f97 RCC: added msik for stm32u5 2024-11-07 13:32:07 +01:00
elagil
e69be0a23b fix: STM32U5 RCC fields 2024-11-06 19:46:55 +01:00
Alexandros Liarokapis
2b7e76efe9 Fix dma nvic issues on dual core lines
This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup.
Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration.
This ensures that each core will only handle the interrupts of the DMA channels that it uses.
2024-08-17 16:54:41 +03:00
Joël Schulz-Ansres
4c55931b6a Remove redundant dsi_phy: None from rcc 2024-05-02 14:58:38 +02:00
Joël Schulz-Ansres
9fe50a7639 Add stm32 dsihost driver 2024-05-02 13:43:42 +02:00
eZio Pan
d9e59e8e42 low power for h5 2024-04-28 00:33:02 +08:00
Dario Nieuwenhuis
95234cddba stm32: autogenerate mux config for all chips. 2024-03-01 23:54:37 +01:00
Dario Nieuwenhuis
c83ab20526 stm32: update metapac. 2024-02-26 03:02:58 +01:00
Dario Nieuwenhuis
489d0be2a2 stm32/rcc: unify naming sysclk field to sys, enum to Sysclk. 2024-02-26 00:00:17 +01:00
Dario Nieuwenhuis
0665e0d452 stm32/rcc: port U5 to new API, add all PLLs, all HSE modes. 2024-02-23 01:24:05 +01:00
Dario Nieuwenhuis
832776d2c7 stm32: update metapac. 2024-02-10 02:50:35 +01:00
Dario Nieuwenhuis
9866847375 stm32: autogenerate clocks struct, enable mux for all chips. 2024-02-02 23:24:34 +01:00
Tyler Gilbert
7944e854dd Fix formatting of comments 2024-01-03 11:07:57 -06:00
Tyler
727906fa04
Update u5.rs
Update comments on p and q divider values to correctly describe what the clock outputs are used for.
2024-01-03 11:04:48 -06:00
Tyler Gilbert
31bf127807 Update STM32 RCC U5 to support P and Q dividers 2024-01-03 10:46:45 -06:00
Dario Nieuwenhuis
4fe344ebc0 stm32/rcc: consistent casing and naming for PLL enums. 2023-11-13 00:52:01 +01:00
Dario Nieuwenhuis
0272deb158 stm32/rcc: add shared code for hsi48 with crs support. 2023-11-05 23:52:54 +01:00
Dario Nieuwenhuis
b9e13cb5d1 stm32/rcc: merge wl into l4/l5. 2023-10-23 00:31:36 +02:00
Dario Nieuwenhuis
412bcad2d1 stm32: rename HSI16 -> HSI 2023-10-22 22:39:55 +02:00
xoviat
0fb677aad7 stm32: update metapac 2023-10-20 20:21:53 -05:00
Dario Nieuwenhuis
aff77d2b65 stm32/rng: add test. 2023-10-16 05:35:29 +02:00
xoviat
b24520579a rcc: ahb/apb -> hclk/pclk 2023-10-15 19:51:35 -05:00
Dario Nieuwenhuis
b91d1eaca0 stm32/rcc: add LSE/LSI to all chips, add RTC to more chips. 2023-10-11 04:12:38 +02:00
Dario Nieuwenhuis
6186fe0807 stm32/rcc: use PLL enums from PAC. 2023-10-09 02:48:22 +02:00
Will Glynn
38e7709a24 stm32: u5: implement >55 MHz clock speeds
This commit allows STM32U5 devices to operate at 160 MHz.

On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster
clocks require using PLL1's R output, though PLL1 can serve other
functions besides using the R output for the system clock. This commit
extracts a public `PllConfig` struct, primarily to place associated
constructors on that type, but also with an eye towards enabling the P
and Q outputs in a later commit.

STM32U5 PLLs have various frequency requirements on each stage: after
the `m` prescaler, after the `n` multiplier, and after the `r` divider.
This commit implements the associated checks as assertions.

This commit fixes clock calculation and PLL register configuration
errors in PLL initialization.

STM32U5 has a PWR peripheral which can be configured to push Vcore into
different voltage ranges. System clocks exceeding 55 MHz require range
2, and system clocks exceeding 110 MHz require range 1. This commit
adds `voltage_range` to `Config` and configures PWR as directed.

The voltage range implies different performance limits on various clock
signals, including inside a PLL. This commit implements voltage range
<-> frequency range checks as assertions, and extracts the
otherwise-repeated MSIS, HSI16, and HSE initialization into private
methods on `Config`.

STM32U5 frequencies above 55 MHz require using the PWR EPOD booster.
The EPOD booster requires configuring a second `m` term for PLL1,
`mboost`, such that it falls in a particular range. (Recall that >50
MHz cannot be reached without PLL1, so there is no scenario where EPOD
is needed but PLL1 is not.) This commit configures and enables the EPOD
booster automatically as required.
2023-10-05 22:13:27 -05:00
Dario Nieuwenhuis
4bfbcd6c72 stm32: use PAC enums for VOS. 2023-09-18 03:15:15 +02:00
xoviat
de2773afdd stm32/rcc: convert bus prescalers to pac enums 2023-09-16 17:41:11 -05:00
Dario Nieuwenhuis
8315cf064e stm32: add stm32wba support. 2023-09-16 04:04:45 +02:00
xoviat
48085939e7 stm32/rcc: rename common to bus 2023-08-27 08:35:13 -05:00
xoviat
2f18770e27 stm32/rcc: extract and combine ahb/apb prescalers 2023-07-30 09:52:30 -05:00
Dario Nieuwenhuis
e892014b65 Update stm32-metapac, includes chiptool changes to use real Rust enums now. 2023-06-29 02:01:33 +02:00
Eric Yanush
13f0c64a8c Fix APB clock calculation for several STM32 families 2023-03-16 21:21:39 -06:00
Dario Nieuwenhuis
041531c829 stm32/rcc: fix u5 pll, add hsi48. 2023-01-11 17:57:22 +01:00
Dario Nieuwenhuis
2649f13dc7 stm32/rcc: fix unnecessary parentheses 2022-08-17 15:03:23 +02:00
Grant Miller
5ecbe5c918 embassy-stm32: Simplify time
- Remove unused `MilliSeconds`, `MicroSeconds`, and `NanoSeconds` types
- Remove `Bps`, `KiloHertz`, and `MegaHertz` types that were only used
for converting to `Hertz`
- Replace all instances of `impl Into<Hertz>` with `Hertz`
- Add `hz`, `khz`, and `mhz` methods to `Hertz`, as well as
free function shortcuts
- Remove `U32Ext` extension trait
2022-07-10 21:46:45 -05:00
chemicstry
1fd5022e72 Refactor IWDG to use LSI frequency from RCC 2022-07-10 20:59:36 +03:00
Dario Nieuwenhuis
88e36a70bd
Update to 2021 edition. (#820) 2022-06-18 02:15:48 +02:00
Dario Nieuwenhuis
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
Dario Nieuwenhuis
2eb0cc5df7 stm32/rcc: remove Rcc struct, RccExt trait.
All the RCC configuration is executed in init().
2022-01-05 00:00:44 +01:00
Dario Nieuwenhuis
b06e705a73 stm32/rcc: change family-specific code from dirs to single files.
Consistent with how other peripherals handle their versions.
2022-01-04 19:28:15 +01:00