499 lines
14 KiB
Rust
499 lines
14 KiB
Rust
#[cfg(not(stm32u5))]
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use pac::adc::vals::{Adcaldif, Boost};
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#[allow(unused)]
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use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
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use pac::adccommon::vals::Presc;
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use super::{
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blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
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};
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use crate::dma::Transfer;
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use crate::time::Hertz;
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use crate::{pac, rcc, Peri};
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/// Default VREF voltage used for sample conversion to millivolts.
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pub const VREF_DEFAULT_MV: u32 = 3300;
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/// VREF voltage used for factory calibration of VREFINTCAL register.
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pub const VREF_CALIB_MV: u32 = 3300;
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/// Max single ADC operation clock frequency
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#[cfg(stm32g4)]
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const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
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#[cfg(stm32h7)]
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const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
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#[cfg(stm32u5)]
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const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
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#[cfg(stm32g4)]
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const VREF_CHANNEL: u8 = 18;
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#[cfg(stm32g4)]
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const TEMP_CHANNEL: u8 = 16;
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#[cfg(stm32h7)]
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const VREF_CHANNEL: u8 = 19;
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#[cfg(stm32h7)]
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const TEMP_CHANNEL: u8 = 18;
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// TODO this should be 14 for H7a/b/35
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#[cfg(not(stm32u5))]
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const VBAT_CHANNEL: u8 = 17;
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#[cfg(stm32u5)]
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const VREF_CHANNEL: u8 = 0;
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#[cfg(stm32u5)]
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const TEMP_CHANNEL: u8 = 19;
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#[cfg(stm32u5)]
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const VBAT_CHANNEL: u8 = 18;
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// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
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/// Internal voltage reference channel.
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pub struct VrefInt;
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impl<T: Instance> AdcChannel<T> for VrefInt {}
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impl<T: Instance> SealedAdcChannel<T> for VrefInt {
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fn channel(&self) -> u8 {
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VREF_CHANNEL
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}
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}
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/// Internal temperature channel.
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pub struct Temperature;
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impl<T: Instance> AdcChannel<T> for Temperature {}
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impl<T: Instance> SealedAdcChannel<T> for Temperature {
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fn channel(&self) -> u8 {
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TEMP_CHANNEL
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}
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}
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/// Internal battery voltage channel.
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pub struct Vbat;
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impl<T: Instance> AdcChannel<T> for Vbat {}
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impl<T: Instance> SealedAdcChannel<T> for Vbat {
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fn channel(&self) -> u8 {
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VBAT_CHANNEL
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}
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}
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// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
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// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
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#[allow(unused)]
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enum Prescaler {
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NotDivided,
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DividedBy2,
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DividedBy4,
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DividedBy6,
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DividedBy8,
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DividedBy10,
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DividedBy12,
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DividedBy16,
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DividedBy32,
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DividedBy64,
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DividedBy128,
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DividedBy256,
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}
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impl Prescaler {
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fn from_ker_ck(frequency: Hertz) -> Self {
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let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
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match raw_prescaler {
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0 => Self::NotDivided,
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1 => Self::DividedBy2,
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2..=3 => Self::DividedBy4,
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4..=5 => Self::DividedBy6,
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6..=7 => Self::DividedBy8,
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8..=9 => Self::DividedBy10,
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10..=11 => Self::DividedBy12,
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_ => unimplemented!(),
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}
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}
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fn divisor(&self) -> u32 {
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match self {
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Prescaler::NotDivided => 1,
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Prescaler::DividedBy2 => 2,
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Prescaler::DividedBy4 => 4,
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Prescaler::DividedBy6 => 6,
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Prescaler::DividedBy8 => 8,
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Prescaler::DividedBy10 => 10,
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Prescaler::DividedBy12 => 12,
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Prescaler::DividedBy16 => 16,
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Prescaler::DividedBy32 => 32,
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Prescaler::DividedBy64 => 64,
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Prescaler::DividedBy128 => 128,
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Prescaler::DividedBy256 => 256,
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}
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}
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fn presc(&self) -> Presc {
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match self {
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Prescaler::NotDivided => Presc::DIV1,
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Prescaler::DividedBy2 => Presc::DIV2,
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Prescaler::DividedBy4 => Presc::DIV4,
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Prescaler::DividedBy6 => Presc::DIV6,
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Prescaler::DividedBy8 => Presc::DIV8,
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Prescaler::DividedBy10 => Presc::DIV10,
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Prescaler::DividedBy12 => Presc::DIV12,
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Prescaler::DividedBy16 => Presc::DIV16,
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Prescaler::DividedBy32 => Presc::DIV32,
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Prescaler::DividedBy64 => Presc::DIV64,
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Prescaler::DividedBy128 => Presc::DIV128,
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Prescaler::DividedBy256 => Presc::DIV256,
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}
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}
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}
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/// Number of samples used for averaging.
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pub enum Averaging {
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Disabled,
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Samples2,
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Samples4,
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Samples8,
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Samples16,
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Samples32,
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Samples64,
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Samples128,
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Samples256,
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Samples512,
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Samples1024,
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}
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impl<'d, T: Instance> Adc<'d, T> {
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/// Create a new ADC driver.
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pub fn new(adc: Peri<'d, T>) -> Self {
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rcc::enable_and_reset::<T>();
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let prescaler = Prescaler::from_ker_ck(T::frequency());
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T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
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let frequency = Hertz(T::frequency().0 / prescaler.divisor());
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info!("ADC frequency set to {} Hz", frequency.0);
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if frequency > MAX_ADC_CLK_FREQ {
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panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 / 1_000_000 );
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}
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#[cfg(stm32h7)]
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{
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let boost = if frequency < Hertz::khz(6_250) {
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Boost::LT6_25
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} else if frequency < Hertz::khz(12_500) {
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Boost::LT12_5
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} else if frequency < Hertz::mhz(25) {
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Boost::LT25
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} else {
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Boost::LT50
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};
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T::regs().cr().modify(|w| w.set_boost(boost));
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}
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let mut s = Self {
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adc,
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sample_time: SampleTime::from_bits(0),
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};
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s.power_up();
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s.configure_differential_inputs();
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s.calibrate();
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blocking_delay_us(1);
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s.enable();
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s.configure();
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s
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}
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fn power_up(&mut self) {
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T::regs().cr().modify(|reg| {
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reg.set_deeppwd(false);
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reg.set_advregen(true);
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});
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blocking_delay_us(10);
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}
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fn configure_differential_inputs(&mut self) {
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T::regs().difsel().modify(|w| {
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for n in 0..20 {
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w.set_difsel(n, Difsel::SINGLE_ENDED);
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}
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});
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}
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fn calibrate(&mut self) {
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T::regs().cr().modify(|w| {
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#[cfg(not(adc_u5))]
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w.set_adcaldif(Adcaldif::SINGLE_ENDED);
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w.set_adcallin(true);
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});
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T::regs().cr().modify(|w| w.set_adcal(true));
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while T::regs().cr().read().adcal() {}
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}
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fn enable(&mut self) {
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T::regs().isr().write(|w| w.set_adrdy(true));
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T::regs().cr().modify(|w| w.set_aden(true));
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while !T::regs().isr().read().adrdy() {}
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T::regs().isr().write(|w| w.set_adrdy(true));
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}
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fn configure(&mut self) {
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// single conversion mode, software trigger
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T::regs().cfgr().modify(|w| {
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w.set_cont(false);
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w.set_exten(Exten::DISABLED);
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});
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}
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/// Enable reading the voltage reference internal channel.
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pub fn enable_vrefint(&self) -> VrefInt {
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T::common_regs().ccr().modify(|reg| {
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reg.set_vrefen(true);
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});
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VrefInt {}
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}
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/// Enable reading the temperature internal channel.
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pub fn enable_temperature(&self) -> Temperature {
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T::common_regs().ccr().modify(|reg| {
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reg.set_vsenseen(true);
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});
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Temperature {}
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}
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/// Enable reading the vbat internal channel.
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pub fn enable_vbat(&self) -> Vbat {
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T::common_regs().ccr().modify(|reg| {
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reg.set_vbaten(true);
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});
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Vbat {}
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}
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/// Set the ADC sample time.
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pub fn set_sample_time(&mut self, sample_time: SampleTime) {
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self.sample_time = sample_time;
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}
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/// Get the ADC sample time.
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pub fn sample_time(&self) -> SampleTime {
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self.sample_time
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}
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/// Set the ADC resolution.
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pub fn set_resolution(&mut self, resolution: Resolution) {
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T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
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}
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/// Set hardware averaging.
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pub fn set_averaging(&mut self, averaging: Averaging) {
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let (enable, samples, right_shift) = match averaging {
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Averaging::Disabled => (false, 0, 0),
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Averaging::Samples2 => (true, 1, 1),
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Averaging::Samples4 => (true, 3, 2),
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Averaging::Samples8 => (true, 7, 3),
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Averaging::Samples16 => (true, 15, 4),
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Averaging::Samples32 => (true, 31, 5),
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Averaging::Samples64 => (true, 63, 6),
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Averaging::Samples128 => (true, 127, 7),
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Averaging::Samples256 => (true, 255, 8),
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Averaging::Samples512 => (true, 511, 9),
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Averaging::Samples1024 => (true, 1023, 10),
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};
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T::regs().cfgr2().modify(|reg| {
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reg.set_rovse(enable);
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reg.set_osvr(samples);
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reg.set_ovss(right_shift);
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})
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}
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/// Perform a single conversion.
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fn convert(&mut self) -> u16 {
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T::regs().isr().modify(|reg| {
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reg.set_eos(true);
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reg.set_eoc(true);
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});
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// Start conversion
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T::regs().cr().modify(|reg| {
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reg.set_adstart(true);
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});
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while !T::regs().isr().read().eos() {
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// spin
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}
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T::regs().dr().read().0 as u16
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}
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/// Read an ADC channel.
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pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
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self.read_channel(channel)
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}
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/// Read one or multiple ADC channels using DMA.
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///
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/// `sequence` iterator and `readings` must have the same length.
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///
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/// Example
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/// ```rust,ignore
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/// use embassy_stm32::adc::{Adc, AdcChannel}
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///
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/// let mut adc = Adc::new(p.ADC1);
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/// let mut adc_pin0 = p.PA0.into();
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/// let mut adc_pin2 = p.PA2.into();
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/// let mut measurements = [0u16; 2];
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///
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/// adc.read_async(
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/// p.DMA2_CH0,
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/// [
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/// (&mut *adc_pin0, SampleTime::CYCLES112),
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/// (&mut *adc_pin2, SampleTime::CYCLES112),
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/// ]
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/// .into_iter(),
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/// &mut measurements,
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/// )
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/// .await;
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/// defmt::info!("measurements: {}", measurements);
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/// ```
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pub async fn read(
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&mut self,
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rx_dma: Peri<'_, impl RxDma<T>>,
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sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
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readings: &mut [u16],
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) {
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assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
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assert!(
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sequence.len() == readings.len(),
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"Sequence length must be equal to readings length"
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);
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assert!(
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sequence.len() <= 16,
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"Asynchronous read sequence cannot be more than 16 in length"
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);
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// Ensure no conversions are ongoing
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Self::cancel_conversions();
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// Set sequence length
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T::regs().sqr1().modify(|w| {
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w.set_l(sequence.len() as u8 - 1);
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});
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// Configure channels and ranks
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for (i, (channel, sample_time)) in sequence.enumerate() {
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Self::configure_channel(channel, sample_time);
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match i {
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0..=3 => {
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T::regs().sqr1().modify(|w| {
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w.set_sq(i, channel.channel());
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});
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}
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4..=8 => {
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T::regs().sqr2().modify(|w| {
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w.set_sq(i - 4, channel.channel());
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});
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}
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9..=13 => {
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T::regs().sqr3().modify(|w| {
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w.set_sq(i - 9, channel.channel());
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});
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}
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14..=15 => {
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T::regs().sqr4().modify(|w| {
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w.set_sq(i - 14, channel.channel());
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});
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}
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_ => unreachable!(),
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}
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}
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// Set continuous mode with oneshot dma.
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// Clear overrun flag before starting transfer.
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T::regs().isr().modify(|reg| {
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reg.set_ovr(true);
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});
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T::regs().cfgr().modify(|reg| {
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reg.set_cont(true);
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reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
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});
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let request = rx_dma.request();
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let transfer = unsafe {
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Transfer::new_read(
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rx_dma,
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request,
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T::regs().dr().as_ptr() as *mut u16,
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readings,
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Default::default(),
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)
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};
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// Start conversion
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T::regs().cr().modify(|reg| {
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reg.set_adstart(true);
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});
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// Wait for conversion sequence to finish.
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transfer.await;
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// Ensure conversions are finished.
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Self::cancel_conversions();
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// Reset configuration.
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T::regs().cfgr().modify(|reg| {
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reg.set_cont(false);
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reg.set_dmngt(Dmngt::from_bits(0));
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});
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}
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fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
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channel.setup();
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let channel = channel.channel();
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Self::set_channel_sample_time(channel, sample_time);
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#[cfg(any(stm32h7, stm32u5))]
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{
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T::regs().cfgr2().modify(|w| w.set_lshift(0));
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T::regs()
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.pcsel()
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.modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
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}
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}
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fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
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Self::configure_channel(channel, self.sample_time);
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T::regs().sqr1().modify(|reg| {
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reg.set_sq(0, channel.channel());
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reg.set_l(0);
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});
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self.convert()
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}
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fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
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let sample_time = sample_time.into();
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if ch <= 9 {
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T::regs().smpr(0).modify(|reg| reg.set_smp(ch as _, sample_time));
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} else {
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T::regs().smpr(1).modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
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}
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}
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fn cancel_conversions() {
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if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
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T::regs().cr().modify(|reg| {
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reg.set_adstp(Adstp::STOP);
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});
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while T::regs().cr().read().adstart() {}
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}
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}
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}
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