379 lines
12 KiB
Rust
379 lines
12 KiB
Rust
use core::ptr::write_volatile;
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use core::sync::atomic::{fence, AtomicBool, Ordering};
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use embassy_sync::waitqueue::AtomicWaker;
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use pac::flash::regs::Sr;
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use super::{get_flash_regions, FlashBank, FlashSector, WRITE_SIZE};
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use crate::_generated::FLASH_SIZE;
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use crate::flash::Error;
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use crate::pac;
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static WAKER: AtomicWaker = AtomicWaker::new();
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static DATA_CACHE_WAS_ENABLED: AtomicBool = AtomicBool::new(false);
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impl FlashSector {
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const fn snb(&self) -> u8 {
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((self.bank as u8) << 4) + self.index_in_bank
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}
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}
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pub(crate) unsafe fn on_interrupt() {
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// Clear IRQ flags
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pac::FLASH.sr().write(|w| {
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w.set_operr(true);
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w.set_eop(true);
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});
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WAKER.wake();
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}
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pub(crate) unsafe fn lock() {
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pac::FLASH.cr().modify(|w| w.set_lock(true));
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}
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pub(crate) unsafe fn unlock() {
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if pac::FLASH.cr().read().lock() {
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pac::FLASH.keyr().write_value(0x4567_0123);
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pac::FLASH.keyr().write_value(0xCDEF_89AB);
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}
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}
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pub(crate) unsafe fn enable_write() {
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assert_eq!(0, WRITE_SIZE % 4);
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save_data_cache_state();
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pac::FLASH.cr().write(|w| {
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w.set_pg(true);
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w.set_psize(pac::flash::vals::Psize::PSIZE32);
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w.set_eopie(true);
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w.set_errie(true);
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});
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}
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pub(crate) unsafe fn disable_write() {
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pac::FLASH.cr().write(|w| {
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w.set_pg(false);
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w.set_eopie(false);
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w.set_errie(false);
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});
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restore_data_cache_state();
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}
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pub(crate) unsafe fn enable_blocking_write() {
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assert_eq!(0, WRITE_SIZE % 4);
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save_data_cache_state();
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pac::FLASH.cr().write(|w| {
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w.set_pg(true);
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w.set_psize(pac::flash::vals::Psize::PSIZE32);
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});
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}
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pub(crate) unsafe fn disable_blocking_write() {
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pac::FLASH.cr().write(|w| w.set_pg(false));
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restore_data_cache_state();
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}
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pub(crate) async unsafe fn write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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write_start(start_address, buf);
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wait_ready().await
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}
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pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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write_start(start_address, buf);
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blocking_wait_ready()
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}
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unsafe fn write_start(start_address: u32, buf: &[u8; WRITE_SIZE]) {
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let mut address = start_address;
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for val in buf.chunks(4) {
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write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
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address += val.len() as u32;
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// prevents parallelism errors
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fence(Ordering::SeqCst);
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}
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}
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pub(crate) async unsafe fn erase_sector(sector: &FlashSector) -> Result<(), Error> {
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save_data_cache_state();
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trace!("Erasing sector number {}", sector.snb());
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pac::FLASH.cr().modify(|w| {
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w.set_ser(true);
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w.set_snb(sector.snb());
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w.set_eopie(true);
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w.set_errie(true);
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});
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pac::FLASH.cr().modify(|w| {
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w.set_strt(true);
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});
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let ret: Result<(), Error> = wait_ready().await;
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pac::FLASH.cr().modify(|w| {
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w.set_eopie(false);
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w.set_errie(false);
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});
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clear_all_err();
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restore_data_cache_state();
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ret
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}
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pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
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save_data_cache_state();
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trace!("Blocking erasing sector number {}", sector.snb());
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pac::FLASH.cr().modify(|w| {
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w.set_ser(true);
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w.set_snb(sector.snb())
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});
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pac::FLASH.cr().modify(|w| {
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w.set_strt(true);
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});
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let ret: Result<(), Error> = blocking_wait_ready();
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clear_all_err();
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restore_data_cache_state();
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ret
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}
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pub(crate) fn clear_all_err() {
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// read and write back the same value.
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// This clears all "write 1 to clear" bits.
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pac::FLASH.sr().modify(|_| {});
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}
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pub(crate) async fn wait_ready() -> Result<(), Error> {
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use core::future::poll_fn;
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use core::task::Poll;
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poll_fn(|cx| {
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WAKER.register(cx.waker());
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let sr = pac::FLASH.sr().read();
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if !sr.bsy() {
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Poll::Ready(get_result(sr))
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} else {
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return Poll::Pending;
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}
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})
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.await
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}
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unsafe fn blocking_wait_ready() -> Result<(), Error> {
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loop {
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let sr = pac::FLASH.sr().read();
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if !sr.bsy() {
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return get_result(sr);
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}
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}
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}
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fn get_result(sr: Sr) -> Result<(), Error> {
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if sr.pgserr() {
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Err(Error::Seq)
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} else if sr.pgperr() {
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Err(Error::Parallelism)
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} else if sr.pgaerr() {
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Err(Error::Unaligned)
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} else if sr.wrperr() {
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Err(Error::Protected)
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} else {
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Ok(())
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}
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}
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fn save_data_cache_state() {
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let dual_bank = unwrap!(get_flash_regions().last()).bank == FlashBank::Bank2;
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if dual_bank {
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// Disable data cache during write/erase if there are two banks, see errata 2.2.12
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let dcen = pac::FLASH.acr().read().dcen();
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DATA_CACHE_WAS_ENABLED.store(dcen, Ordering::Relaxed);
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if dcen {
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pac::FLASH.acr().modify(|w| w.set_dcen(false));
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}
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}
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}
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fn restore_data_cache_state() {
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let dual_bank = unwrap!(get_flash_regions().last()).bank == FlashBank::Bank2;
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if dual_bank {
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// Restore data cache if it was enabled
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let dcen = DATA_CACHE_WAS_ENABLED.load(Ordering::Relaxed);
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if dcen {
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// Reset data cache before we enable it again
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pac::FLASH.acr().modify(|w| w.set_dcrst(true));
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pac::FLASH.acr().modify(|w| w.set_dcrst(false));
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pac::FLASH.acr().modify(|w| w.set_dcen(true))
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}
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}
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}
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pub(crate) fn assert_not_corrupted_read(end_address: u32) {
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#[allow(unused)]
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const REVISION_3: u16 = 0x2001;
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#[allow(unused)]
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let second_bank_read =
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unwrap!(get_flash_regions().last()).bank == FlashBank::Bank2 && end_address > (FLASH_SIZE / 2) as u32;
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#[cfg(any(
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feature = "stm32f427ai",
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feature = "stm32f427ii",
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feature = "stm32f427vi",
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feature = "stm32f427zi",
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feature = "stm32f429ai",
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feature = "stm32f429bi",
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feature = "stm32f429ii",
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feature = "stm32f429ni",
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feature = "stm32f429vi",
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feature = "stm32f429zi",
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feature = "stm32f437ai",
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feature = "stm32f437ii",
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feature = "stm32f437vi",
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feature = "stm32f437zi",
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feature = "stm32f439ai",
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feature = "stm32f439bi",
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feature = "stm32f439ii",
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feature = "stm32f439ni",
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feature = "stm32f439vi",
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feature = "stm32f439zi",
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))]
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if second_bank_read && pac::DBGMCU.idcode().read().rev_id() < REVISION_3 && !pa12_is_output_pull_low() {
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panic!("Read corruption for stm32f42xxI and stm32f43xxI when PA12 is in use for chips below revision 3, see errata 2.2.11");
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}
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#[cfg(any(
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feature = "stm32f427ag",
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feature = "stm32f427ig",
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feature = "stm32f427vg",
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feature = "stm32f427zg",
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feature = "stm32f429ag",
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feature = "stm32f429bg",
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feature = "stm32f429ig",
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feature = "stm32f429ng",
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feature = "stm32f429vg",
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feature = "stm32f429zg",
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feature = "stm32f437ig",
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feature = "stm32f437vg",
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feature = "stm32f437zg",
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feature = "stm32f439bg",
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feature = "stm32f439ig",
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feature = "stm32f439ng",
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feature = "stm32f439vg",
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feature = "stm32f439zg",
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))]
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if second_bank_read && pac::DBGMCU.idcode().read().rev_id() < REVISION_3 && !pa12_is_output_pull_low() {
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panic!("Read corruption for stm32f42xxG and stm32f43xxG in dual bank mode when PA12 is in use for chips below revision 3, see errata 2.2.11");
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}
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}
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#[allow(unused)]
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fn pa12_is_output_pull_low() -> bool {
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use pac::gpio::vals;
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use pac::GPIOA;
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const PIN: usize = 12;
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GPIOA.moder().read().moder(PIN) == vals::Moder::OUTPUT
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&& GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULL_DOWN
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&& GPIOA.odr().read().odr(PIN) == vals::Odr::LOW
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use crate::flash::{get_sector, FlashBank};
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#[test]
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#[cfg(stm32f429)]
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fn can_get_sector() {
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const SMALL_SECTOR_SIZE: u32 = 16 * 1024;
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const MEDIUM_SECTOR_SIZE: u32 = 64 * 1024;
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const LARGE_SECTOR_SIZE: u32 = 128 * 1024;
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if !cfg!(feature = "dual-bank") {
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let assert_sector = |snb: u8, index_in_bank: u8, start: u32, size: u32, address: u32| {
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let sector = get_sector(address, crate::flash::get_flash_regions());
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assert_eq!(snb, sector.snb());
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assert_eq!(
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FlashSector {
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bank: sector.bank,
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index_in_bank,
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start,
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size
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},
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sector
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);
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};
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assert_sector(0x00, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
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assert_sector(0x00, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
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assert_sector(0x03, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
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assert_sector(0x03, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
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assert_sector(0x04, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
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assert_sector(0x04, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
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assert_sector(0x05, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
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assert_sector(0x05, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
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assert_sector(0x0B, 11, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080E_0000);
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assert_sector(0x0B, 11, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
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} else {
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let assert_sector = |snb: u8, bank: FlashBank, index_in_bank: u8, start: u32, size: u32, address: u32| {
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let sector = get_sector(address, crate::flash::get_flash_regions());
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assert_eq!(snb, sector.snb());
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assert_eq!(
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FlashSector {
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bank,
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index_in_bank,
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start,
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size
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},
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sector
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)
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};
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assert_sector(0x00, FlashBank::Bank1, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
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assert_sector(0x00, FlashBank::Bank1, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
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assert_sector(0x03, FlashBank::Bank1, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
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assert_sector(0x03, FlashBank::Bank1, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
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assert_sector(0x04, FlashBank::Bank1, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
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assert_sector(0x04, FlashBank::Bank1, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
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assert_sector(0x05, FlashBank::Bank1, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
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assert_sector(0x05, FlashBank::Bank1, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
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assert_sector(0x07, FlashBank::Bank1, 7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0806_0000);
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assert_sector(0x07, FlashBank::Bank1, 7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0807_FFFF);
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assert_sector(0x10, FlashBank::Bank2, 0, 0x0808_0000, SMALL_SECTOR_SIZE, 0x0808_0000);
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assert_sector(0x10, FlashBank::Bank2, 0, 0x0808_0000, SMALL_SECTOR_SIZE, 0x0808_3FFF);
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assert_sector(0x13, FlashBank::Bank2, 3, 0x0808_C000, SMALL_SECTOR_SIZE, 0x0808_C000);
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assert_sector(0x13, FlashBank::Bank2, 3, 0x0808_C000, SMALL_SECTOR_SIZE, 0x0808_FFFF);
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assert_sector(0x14, FlashBank::Bank2, 4, 0x0809_0000, MEDIUM_SECTOR_SIZE, 0x0809_0000);
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assert_sector(0x14, FlashBank::Bank2, 4, 0x0809_0000, MEDIUM_SECTOR_SIZE, 0x0809_FFFF);
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assert_sector(0x15, FlashBank::Bank2, 5, 0x080A_0000, LARGE_SECTOR_SIZE, 0x080A_0000);
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assert_sector(0x15, FlashBank::Bank2, 5, 0x080A_0000, LARGE_SECTOR_SIZE, 0x080B_FFFF);
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assert_sector(0x17, FlashBank::Bank2, 7, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080E_0000);
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assert_sector(0x17, FlashBank::Bank2, 7, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
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}
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}
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}
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#[cfg(all(bank_setup_configurable))]
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pub(crate) fn check_bank_setup() {
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if cfg!(feature = "single-bank") && pac::FLASH.optcr().read().db1m() {
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panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use dual-bank config");
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}
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if cfg!(feature = "dual-bank") && !pac::FLASH.optcr().read().db1m() {
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panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use single-bank config");
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}
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}
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