143 lines
3.7 KiB
Rust
143 lines
3.7 KiB
Rust
use core::ptr::write_volatile;
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use core::sync::atomic::{fence, AtomicBool, Ordering};
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use pac::flash::regs::Sr;
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use super::{FlashBank, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
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use crate::flash::Error;
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use crate::pac;
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static DATA_CACHE_WAS_ENABLED: AtomicBool = AtomicBool::new(false);
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impl FlashSector {
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const fn snb(&self) -> u8 {
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((self.bank as u8) << 4) + self.index_in_bank
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}
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}
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pub(crate) const fn is_default_layout() -> bool {
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true
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}
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pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
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&FLASH_REGIONS
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}
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pub(crate) unsafe fn lock() {
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pac::FLASH.cr().modify(|w| w.set_lock(true));
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}
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pub(crate) unsafe fn unlock() {
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if pac::FLASH.cr().read().lock() {
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pac::FLASH.keyr().write_value(0x4567_0123);
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pac::FLASH.keyr().write_value(0xCDEF_89AB);
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}
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}
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pub(crate) unsafe fn enable_blocking_write() {
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assert_eq!(0, WRITE_SIZE % 4);
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save_data_cache_state();
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pac::FLASH.cr().write(|w| {
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w.set_pg(true);
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w.set_psize(pac::flash::vals::Psize::PSIZE32);
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});
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}
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pub(crate) unsafe fn disable_blocking_write() {
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pac::FLASH.cr().write(|w| w.set_pg(false));
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restore_data_cache_state();
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}
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pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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write_start(start_address, buf);
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blocking_wait_ready()
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}
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unsafe fn write_start(start_address: u32, buf: &[u8; WRITE_SIZE]) {
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let mut address = start_address;
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for val in buf.chunks(4) {
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write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
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address += val.len() as u32;
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// prevents parallelism errors
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fence(Ordering::SeqCst);
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}
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}
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pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
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save_data_cache_state();
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trace!("Blocking erasing sector number {}", sector.snb());
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pac::FLASH.cr().modify(|w| {
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w.set_ser(true);
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w.set_snb(sector.snb())
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});
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pac::FLASH.cr().modify(|w| {
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w.set_strt(true);
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});
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let ret: Result<(), Error> = blocking_wait_ready();
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clear_all_err();
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restore_data_cache_state();
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ret
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}
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pub(crate) unsafe fn clear_all_err() {
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// read and write back the same value.
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// This clears all "write 1 to clear" bits.
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pac::FLASH.sr().modify(|_| {});
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}
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unsafe fn blocking_wait_ready() -> Result<(), Error> {
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loop {
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let sr = pac::FLASH.sr().read();
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if !sr.bsy() {
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return get_result(sr);
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}
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}
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}
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fn get_result(sr: Sr) -> Result<(), Error> {
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if sr.pgserr() {
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Err(Error::Seq)
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} else if sr.pgperr() {
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Err(Error::Parallelism)
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} else if sr.pgaerr() {
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Err(Error::Unaligned)
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} else if sr.wrperr() {
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Err(Error::Protected)
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} else {
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Ok(())
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}
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}
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fn save_data_cache_state() {
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let dual_bank = unwrap!(get_flash_regions().last()).bank == FlashBank::Bank2;
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if dual_bank {
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// Disable data cache during write/erase if there are two banks, see errata 2.2.12
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let dcen = pac::FLASH.acr().read().dcen();
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DATA_CACHE_WAS_ENABLED.store(dcen, Ordering::Relaxed);
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if dcen {
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pac::FLASH.acr().modify(|w| w.set_dcen(false));
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}
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}
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}
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fn restore_data_cache_state() {
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let dual_bank = unwrap!(get_flash_regions().last()).bank == FlashBank::Bank2;
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if dual_bank {
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// Restore data cache if it was enabled
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let dcen = DATA_CACHE_WAS_ENABLED.load(Ordering::Relaxed);
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if dcen {
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// Reset data cache before we enable it again
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pac::FLASH.acr().modify(|w| w.set_dcrst(true));
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pac::FLASH.acr().modify(|w| w.set_dcrst(false));
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pac::FLASH.acr().modify(|w| w.set_dcen(true))
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}
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}
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}
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