124 lines
4.0 KiB
Rust
124 lines
4.0 KiB
Rust
use core::ptr::write_volatile;
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use core::sync::atomic::{fence, Ordering};
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use cortex_m::interrupt;
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use super::{FlashSector, WRITE_SIZE};
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use crate::flash::Error;
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use crate::pac;
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pub(crate) unsafe fn lock() {
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pac::FLASH.cr().modify(|w| w.set_lock(true));
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}
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pub(crate) unsafe fn unlock() {
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// Wait, while the memory interface is busy.
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wait_busy();
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// Unlock flash
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if pac::FLASH.cr().read().lock() {
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pac::FLASH.keyr().write_value(0x4567_0123);
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pac::FLASH.keyr().write_value(0xCDEF_89AB);
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}
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}
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pub(crate) unsafe fn enable_blocking_write() {
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assert_eq!(0, WRITE_SIZE % 4);
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pac::FLASH.cr().write(|w| w.set_pg(true));
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}
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pub(crate) unsafe fn disable_blocking_write() {
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pac::FLASH.cr().write(|w| w.set_pg(false));
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}
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pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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let mut address = start_address;
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for val in buf.chunks(4) {
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write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
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address += val.len() as u32;
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// prevents parallelism errors
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fence(Ordering::SeqCst);
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}
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wait_ready_blocking()
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}
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pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
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let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
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wait_busy();
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clear_all_err();
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interrupt::free(|_| {
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pac::FLASH.cr().modify(|w| {
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w.set_per(true);
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#[cfg(any(flash_g0x0, flash_g0x1, flash_g4c3))]
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w.set_bker(sector.bank == crate::flash::FlashBank::Bank2);
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#[cfg(flash_g0x0)]
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w.set_pnb(idx as u16);
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#[cfg(not(flash_g0x0))]
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w.set_pnb(idx as u8);
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w.set_strt(true);
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});
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});
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let ret: Result<(), Error> = wait_ready_blocking();
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pac::FLASH.cr().modify(|w| w.set_per(false));
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ret
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}
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pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
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while pac::FLASH.sr().read().bsy() {}
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let sr = pac::FLASH.sr().read();
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if sr.progerr() {
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return Err(Error::Prog);
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}
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if sr.wrperr() {
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return Err(Error::Protected);
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}
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if sr.pgaerr() {
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return Err(Error::Unaligned);
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}
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Ok(())
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}
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pub(crate) unsafe fn clear_all_err() {
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// read and write back the same value.
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// This clears all "write 1 to clear" bits.
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pac::FLASH.sr().modify(|_| {});
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}
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#[cfg(any(flash_g0x0, flash_g0x1))]
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fn wait_busy() {
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while pac::FLASH.sr().read().bsy() | pac::FLASH.sr().read().bsy2() {}
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}
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#[cfg(not(any(flash_g0x0, flash_g0x1)))]
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fn wait_busy() {
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while pac::FLASH.sr().read().bsy() {}
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}
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#[cfg(all(bank_setup_configurable, any(flash_g4c2, flash_g4c3, flash_g4c4)))]
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pub(crate) fn check_bank_setup() {
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if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dbank() {
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panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config");
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}
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if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dbank() {
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panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config");
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}
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}
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#[cfg(all(bank_setup_configurable, flash_g0x1))]
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pub(crate) fn check_bank_setup() {
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if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dual_bank() {
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panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use dual-bank config");
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}
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if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dual_bank() {
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panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use single-bank config");
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}
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}
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