Adam Greig 2218d30c80 STM32: Remove vestigal build.rs cfgs, add new flashsize_X and package_X cfgs, use in F3 RCC

2023-11-25 00:29:45 +01:00

..

bd.rs

rcc: ahb/apb -> hclk/pclk

2023-10-15 19:51:35 -05:00

c0.rs

stm32: update metapac

2023-10-16 20:04:10 -05:00

f0.rs

stm32: update metapac

2023-10-17 20:31:44 -05:00

f1.rs

stm32: update metapac

2023-10-20 20:21:53 -05:00

f3.rs

STM32: Remove vestigal build.rs cfgs, add new flashsize_X and package_X cfgs, use in F3 RCC

2023-11-25 00:29:45 +01:00

f.rs

stm32/rcc: unify f2 into f4/f7.

2023-11-13 01:59:33 +01:00

g0.rs

stm32/rcc: consistent casing and naming for PLL enums.

2023-11-13 00:52:01 +01:00

g4.rs

stm32/rcc: consistent casing and naming for PLL enums.

2023-11-13 00:52:01 +01:00

h.rs

PR feedback

2023-11-19 15:56:34 -08:00

hsi48.rs

stm32/rcc: add shared code for hsi48 with crs support.

2023-11-05 23:52:54 +01:00

l.rs

stm32/rcc: unify l0l1 and l4l5.

2023-11-13 01:05:07 +01:00

mco.rs

stm32: implement MCO for all chips.

2023-10-07 01:15:24 +02:00

mod.rs

stm32/rcc: unify f2 into f4/f7.

2023-11-13 01:59:33 +01:00

u5.rs

stm32/rcc: consistent casing and naming for PLL enums.

2023-11-13 00:52:01 +01:00

wba.rs

stm32/rcc: consistent casing and naming for PLL enums.

2023-11-13 00:52:01 +01:00