Adam Greig
|
2218d30c80
|
STM32: Remove vestigal build.rs cfgs, add new flashsize_X and package_X cfgs, use in F3 RCC
|
2023-11-25 00:29:45 +01:00 |
|
RobertTDowling
|
7f258cd3c4
|
PR feedback
|
2023-11-19 15:56:34 -08:00 |
|
RobertTDowling
|
4947b13615
|
stm32h7 ADC: Fix stalled clock in default h7 config
|
2023-11-15 17:11:16 -08:00 |
|
Dario Nieuwenhuis
|
ace5221080
|
stm32/rcc: unify f2 into f4/f7.
|
2023-11-13 01:59:33 +01:00 |
|
Dario Nieuwenhuis
|
2376b3bdfa
|
stm32/rcc: fix pll enum naming on f4, f7.
|
2023-11-13 01:56:50 +01:00 |
|
Dario Nieuwenhuis
|
066dc297ed
|
stm32/rcc: unify l0l1 and l4l5.
|
2023-11-13 01:05:07 +01:00 |
|
Dario Nieuwenhuis
|
4fe344ebc0
|
stm32/rcc: consistent casing and naming for PLL enums.
|
2023-11-13 00:52:01 +01:00 |
|
eZio Pan
|
8f543062aa
|
check PLL settings before set VOS
|
2023-11-06 18:30:59 +08:00 |
|
Dario Nieuwenhuis
|
b8679c0cc8
|
stm32/rcc: set highest VOS on some F4s with no overdrive.
|
2023-11-06 03:37:39 +01:00 |
|
Dario Nieuwenhuis
|
0272deb158
|
stm32/rcc: add shared code for hsi48 with crs support.
|
2023-11-05 23:52:54 +01:00 |
|
Dario Nieuwenhuis
|
8911a4d855
|
stm32/rcc: switch to modern api for l0, l1.
|
2023-11-05 03:06:13 +01:00 |
|
xoviat
|
3f2abd4fd5
|
Merge branch 'main' of github.com:embassy-rs/embassy into low-power
|
2023-11-04 13:51:11 -05:00 |
|
xoviat
|
dc467e89a0
|
stm32: compute stop mode and workaround rtt test bug
|
2023-11-04 13:49:54 -05:00 |
|
xoviat
|
a904538555
|
stm32/rcc: revert part of #2106
|
2023-11-01 17:27:33 -05:00 |
|
shakencodes
|
bc07539133
|
Fix missed field in cfg'd code
|
2023-11-01 13:30:04 -07:00 |
|
shakencodes
|
b4a82b7ed4
|
Correct adc_clock_source for all µprocs in l4l5.rs
|
2023-11-01 13:22:50 -07:00 |
|
shakencodes
|
e2688dda22
|
Eliminates redefinition of AdcClockSource
|
2023-11-01 12:06:19 -07:00 |
|
shakencodes
|
d0d8585e4c
|
Reinstate rcc::Config adc_clock_source field
|
2023-11-01 11:46:17 -07:00 |
|
xoviat
|
e8a3cfaed6
|
stm32/low-power: refactor refcount
|
2023-10-25 19:07:31 -05:00 |
|
xoviat
|
17b4cf8ce7
|
Merge pull request #2106 from xoviat/fix-stop-2
stm32: fix low-power test
|
2023-10-23 21:29:36 +00:00 |
|
xoviat
|
df4aa0fe25
|
stm32: fix low-power test
|
2023-10-23 16:26:34 -05:00 |
|
Dario Nieuwenhuis
|
a39ae12edc
|
stm32/rcc: misc cleanups.
|
2023-10-23 17:36:21 +02:00 |
|
Dario Nieuwenhuis
|
0ef1cb29f7
|
stm32/rcc: merge wb into l4/l5.
|
2023-10-23 17:36:21 +02:00 |
|
Dario Nieuwenhuis
|
b9e13cb5d1
|
stm32/rcc: merge wl into l4/l5.
|
2023-10-23 00:31:36 +02:00 |
|
Dario Nieuwenhuis
|
412bcad2d1
|
stm32: rename HSI16 -> HSI
|
2023-10-22 22:39:55 +02:00 |
|
Dario Nieuwenhuis
|
62e1e1637c
|
Merge pull request #2097 from embassy-rs/rcc-no-spaghetti
stm32/tests: add stm32h753zi, stm32h7a3zi.
|
2023-10-21 02:49:12 +00:00 |
|
Dario Nieuwenhuis
|
3d03c18d4f
|
stm32/tests: add stm32h753zi, stm32h7a3zi.
|
2023-10-21 04:46:45 +02:00 |
|
xoviat
|
0fb677aad7
|
stm32: update metapac
|
2023-10-20 20:21:53 -05:00 |
|
eZio Pan
|
241488ef1c
|
bypass ODEN if chip doesn't have it
|
2023-10-18 19:42:31 +08:00 |
|
Dario Nieuwenhuis
|
f20f170b1f
|
stm32/rcc: refactor and unify f4 into f7.
|
2023-10-18 05:11:31 +02:00 |
|
Dario Nieuwenhuis
|
67010d123c
|
stm32/rcc: refactor f7.
|
2023-10-18 05:01:11 +02:00 |
|
Dario Nieuwenhuis
|
361fde35cf
|
stm32/rcc: wait for mux switch.
|
2023-10-18 04:32:18 +02:00 |
|
Dario Nieuwenhuis
|
7ce3b19389
|
stm32/rcc: remove unused enum.
|
2023-10-18 04:32:18 +02:00 |
|
xoviat
|
bbd12c9372
|
stm32: update metapac
|
2023-10-17 20:31:44 -05:00 |
|
xoviat
|
683d5c3066
|
Merge pull request #2077 from xoviat/rcc
stm32: update metapac
|
2023-10-17 01:05:18 +00:00 |
|
xoviat
|
a3574e519a
|
stm32: update metapac
|
2023-10-16 20:04:10 -05:00 |
|
Grant Miller
|
e7aeb9b29f
|
stm32f1: Keep flash prefetch enabled
|
2023-10-16 19:23:01 -05:00 |
|
Dario Nieuwenhuis
|
aff77d2b65
|
stm32/rng: add test.
|
2023-10-16 05:35:29 +02:00 |
|
Dario Nieuwenhuis
|
18e96898ea
|
stm32/rcc: unify L4 and L5.
|
2023-10-16 04:00:51 +02:00 |
|
Dario Nieuwenhuis
|
5c5e681819
|
stm32/rcc: add better support for L4/L4+ differences.
|
2023-10-16 03:23:43 +02:00 |
|
xoviat
|
b24520579a
|
rcc: ahb/apb -> hclk/pclk
|
2023-10-15 19:51:35 -05:00 |
|
xoviat
|
1fc35c753b
|
rcc: update pll clock naming
|
2023-10-15 15:10:42 -05:00 |
|
xoviat
|
4a156df7a1
|
stm32: expand rcc mux to g4 and h7
|
2023-10-14 23:33:57 -05:00 |
|
Dario Nieuwenhuis
|
8a10948ce9
|
stm32/rcc: port L4 to the "flattened" API like h5/h7.
|
2023-10-15 03:08:49 +02:00 |
|
Dario Nieuwenhuis
|
3bfbf2697f
|
stm32/rcc: remove unused lse/lsi fields in h7
|
2023-10-15 01:48:27 +02:00 |
|
xoviat
|
824556c9c8
|
rcc: remove mux_prefix from clocks
|
2023-10-14 12:51:45 -05:00 |
|
xoviat
|
3264941c1b
|
rcc mux: update metapac
|
2023-10-13 23:06:32 -05:00 |
|
Dario Nieuwenhuis
|
97ca0e77bf
|
stm32: avoid creating many tiny critical sections in init.
Saves 292 bytes on stm32f0 bilnky with max optimizations (from 3132 to 2840).
|
2023-10-12 16:20:34 +02:00 |
|
pbert
|
ecdd7c0e2f
|
enable clock first
|
2023-10-12 11:04:44 +02:00 |
|
pbert
|
f65a96c541
|
STM32: combine RccPeripherals reset() and enable() to reset_and_enable()
|
2023-10-12 11:04:19 +02:00 |
|