Dario Nieuwenhuis
c46172acac
stm32: remove pointer-to-pointer-to-registers.
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in chiptool pacs the register block struct is already a pointer, so
using pointers to it is redundant.
2024-05-30 13:07:18 +02:00
Aurélien Jacobs
ec6cfc1f21
stm32: ensure the core runs on HSI clock while setting up rcc
2024-05-27 17:31:29 +02:00
Dario Nieuwenhuis
7a26cc3764
Merge pull request #2786 from andelf/fix/stm32wl-msi-crash
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Fix crash caused by using higher MSI range as sysclk on STM32WL
2024-05-21 22:07:50 +00:00
Dario Nieuwenhuis
5ecc9b805d
Merge pull request #2829 from aurelj/stm32-rcc-hsi
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stm32: ensure the core runs on HSI clock while setting up rcc
2024-05-21 22:06:24 +00:00
Dario Nieuwenhuis
6a508b3210
stm32: use funcs for info/state, const for ENABLE_BIT.
2024-05-21 01:24:10 +02:00
Dario Nieuwenhuis
eeb6ffce4c
stm32/rcc: add ClockEnableBit struct.
2024-05-20 23:37:20 +02:00
Joël Schulz-Ansres
4c55931b6a
Remove redundant dsi_phy: None from rcc
2024-05-02 14:58:38 +02:00
Joël Schulz-Ansres
9fe50a7639
Add stm32 dsihost driver
2024-05-02 13:43:42 +02:00
Dario Nieuwenhuis
fb67fe0a6c
stm32: add support for STM32H7[RS] "bootflash line", add HIL tests.
2024-05-01 02:24:45 +02:00
Dario Nieuwenhuis
6f44d7a9df
stm32: update metapac. Adds U5 LPDMA, fixes ADC_COMMONs.
2024-04-29 20:52:27 +02:00
eZio Pan
d9e59e8e42
low power for h5
2024-04-28 00:33:02 +08:00
Aurélien Jacobs
10ee1c1ae8
stm32: ensure the core runs on HSI clock while setting up rcc
2024-04-16 23:36:47 +02:00
Dario Nieuwenhuis
65c085ce91
Add stm32u0 support.
2024-04-14 22:29:07 +02:00
chemicstry
64b806db0b
Expose RCC enable and disable methods
2024-04-12 18:07:44 +03:00
Andelf
803b76df86
Fix crash caused by using higher MSI on STM32WL
2024-04-08 01:23:49 +08:00
Dillon McEwan
2ad82c2adf
Fix 'clocok' typo in RCC docs
2024-04-05 10:07:15 -07:00
eZio Pan
cf11d28d62
stm32 H5: LSE low drive mode is not functional
2024-03-27 00:55:44 +08:00
Dario Nieuwenhuis
2bca875b5f
stm32: use private_bounds for sealed traits.
2024-03-23 01:38:51 +01:00
Dominic
71179fa818
Check for CPU_FREQ_BOOST
2024-03-09 11:55:09 +01:00
Dominic
fadffc5061
Fix incorrect D1CPRE max for STM32H7 RM0468
2024-03-09 11:55:09 +01:00
Tomas Barton
bb3711bbf9
update stm32c0 HSI frequency
2024-03-07 06:51:32 -08:00
Dario Nieuwenhuis
ae266f3bf5
stm32/rcc: port c0 to new api. Add c0 HSIKER/HSISYS support.
2024-03-04 00:08:14 +01:00
Dario Nieuwenhuis
c8c4b0b701
stm32/rcc: port g0 to new api.
2024-03-04 00:04:06 +01:00
Dario Nieuwenhuis
b4567bb8c5
stm32/rcc: g4: consistent PllSource, add pll pqr limits, simplify a bit.
2024-03-04 00:04:06 +01:00
Dario Nieuwenhuis
95234cddba
stm32: autogenerate mux config for all chips.
2024-03-01 23:54:37 +01:00
Maia
b7e0964a07
added FDCANSEL logic for H7
2024-02-27 11:07:05 -08:00
Dario Nieuwenhuis
c83ab20526
stm32: update metapac.
2024-02-26 03:02:58 +01:00
Eli Orona
2dfd66b7c4
🤦
2024-02-25 16:25:42 -08:00
Eli Orona
7dbae799dc
Rust FMT
2024-02-25 16:24:52 -08:00
Eli Orona
c23b59bdc8
Add pll1_p_mul_2 clock.
2024-02-25 16:12:32 -08:00
Dario Nieuwenhuis
489d0be2a2
stm32/rcc: unify naming sysclk field to sys, enum to Sysclk.
2024-02-26 00:00:17 +01:00
Dario Nieuwenhuis
497515ed57
Merge pull request #2583 from OroArmor/tim_pll_clk
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Enable PLL Clocks for TIMx peripherals on STM32F3xx Chips
2024-02-25 22:45:48 +00:00
Eli Orona
394abda092
Fix report with the same name
2024-02-24 12:58:38 -08:00
Eli Orona
e79d2dd756
Move to internal mod and re-export the enums
2024-02-24 12:54:58 -08:00
Dario Nieuwenhuis
f77d59500e
Merge pull request #2618 from barnabywalters/g4rcc
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[embassy-stm32] G4 RCC refactor amendments and additions
2024-02-23 13:05:01 +00:00
Barnaby Walters
b091ffcb55
[embassy-stm32] G4 RCC refactor amendments and additions
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* Added assertions for a variety of clock frequencies, based on the reference manual and
stm32g474 datasheet. The family and numbers are consistent enough that I’m assuming
these numbers will work for the other chips.
* Corrected value of pll1_q in set_clocks call, added pll1_r value
2024-02-23 01:59:24 +01:00
Dario Nieuwenhuis
a6a5d9913c
Merge branch 'main' into stm32l0-reset-rtc
2024-02-23 01:45:10 +01:00
Dario Nieuwenhuis
0665e0d452
stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.
2024-02-23 01:24:05 +01:00
Dario Nieuwenhuis
475dea0208
stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.
2024-02-23 00:18:24 +01:00
Eli Orona
88e29608ed
Rust fmt
2024-02-20 17:59:51 -08:00
Eli Orona
2ee9b37373
Move to a single Mux Struct.
2024-02-20 17:54:35 -08:00
fe1es
5b7e2d8826
stm32/rcc: reset RTC on stm32l0
2024-02-19 15:25:24 +09:00
Eli Orona
e99ef49611
Move to auto-generated based system.
2024-02-16 19:57:00 -08:00
Eli Orona
c99c4a01a9
Update f013.rs
2024-02-16 16:47:38 -08:00
Eli Orona
7592e8be6e
Fix build
2024-02-16 16:45:58 -08:00
Eli Orona
77739faaeb
Rustfmt
2024-02-16 16:42:19 -08:00
Eli Orona
370db9fb06
Update f013.rs
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Add stm32f398
2024-02-16 16:39:23 -08:00
Dario Nieuwenhuis
9352621058
Merge pull request #2579 from barnabywalters/g4rcc
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[embassy-stm32]: stm32g4 RCC refactor
2024-02-16 23:38:49 +00:00
Barnaby Walters
6d7458dac7
Refinements
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* Implemented boost mode dance (RM0440 p234-245, 6.5.1)
* Enabled boost mode in usb_serial example, tested on hardware
* Removed hard requirement of a valid 48MHz source (HSI48 is checked if
requested, PLL passed through as-is and assumed to be valid)
* Used calc_pclk to calculate APB frequencies
* Refactored 48MHz configuration code to remove unnecessary let and block
* Renamed ahb_freq to hclk for clarity and consistency
2024-02-17 00:30:16 +01:00
Barnaby Walters
a24087c36c
Configured SYSCLK after boost mode, added comments
2024-02-16 21:52:58 +01:00
