Move to auto-generated based system.
This commit is contained in:
Eli Orona
parent
c99c4a01a9
commit
e99ef49611
@ -430,6 +430,8 @@ fn main() {
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let mut clock_names = BTreeSet::new();
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let mut rcc_cfgr_regs = BTreeMap::new();
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for p in METADATA.peripherals {
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if !singletons.contains(&p.name.to_string()) {
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continue;
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@ -508,6 +510,16 @@ fn main() {
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let field_name = format_ident!("{}", field_name);
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let enum_name = format_ident!("{}", enum_name);
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if !rcc_cfgr_regs.contains_key(mux.register) {
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rcc_cfgr_regs.insert(mux.register, Vec::new());
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}
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rcc_cfgr_regs.get_mut(mux.register).unwrap().push((
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fieldset_name.clone(),
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field_name.clone(),
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enum_name.clone(),
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));
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let match_arms: TokenStream = enumm
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.variants
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.iter()
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@ -590,6 +602,63 @@ fn main() {
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}
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}
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for (rcc_cfgr_reg, fields) in rcc_cfgr_regs {
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println!("cargo:rustc-cfg={}", rcc_cfgr_reg.to_ascii_lowercase());
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let struct_fields: Vec<_> = fields
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.iter()
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.map(|(_fieldset, fieldname, enum_name)| {
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quote! {
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pub #fieldname: Option<crate::pac::rcc::vals::#enum_name>
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}
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})
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.collect();
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let field_names: Vec<_> = fields
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.iter()
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.map(|(_fieldset, fieldname, _enum_name)| fieldname)
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.collect();
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let inits: Vec<_> = fields
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.iter()
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.map(|(fieldset, fieldname, _enum_name)| {
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let setter = format_ident!("set_{}", fieldname);
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quote! {
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match self.#fieldname {
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None => {}
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Some(val) => {
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crate::pac::RCC.#fieldset()
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.modify(|w| w.#setter(val));
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}
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};
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}
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})
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.collect();
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let cfgr_reg = format_ident!("{}", rcc_cfgr_reg);
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g.extend(quote! {
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#[derive(Clone, Copy)]
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pub struct #cfgr_reg {
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#( #struct_fields, )*
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}
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impl Default for #cfgr_reg {
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fn default() -> Self {
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Self {
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#( #field_names: None, )*
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}
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}
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}
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impl #cfgr_reg {
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pub fn init(self) {
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#( #inits )*
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}
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}
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});
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}
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// Generate RCC
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clock_names.insert("sys".to_string());
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clock_names.insert("rtc".to_string());
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@ -74,116 +74,6 @@ pub enum HrtimClockSource {
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PllClk,
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}
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#[cfg(all(stm32f3, not(rcc_f37)))]
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#[derive(Clone, Copy, PartialEq, Eq)]
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pub enum TimClockSource {
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PClk2,
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PllClk,
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}
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#[cfg(all(stm32f3, not(rcc_f37)))]
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#[derive(Clone, Copy)]
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pub struct TimClockSources {
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pub tim1: TimClockSource,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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all(stm32f302, any(package_D, package_E)),
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stm32f398
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))]
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pub tim2: TimClockSource,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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all(stm32f302, any(package_D, package_E)),
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stm32f398
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))]
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pub tim34: TimClockSource,
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#[cfg(any(
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all(stm32f303, any(package_B, package_C, package_D, package_E)),
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stm32f358,
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stm32f398
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))]
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pub tim8: TimClockSource,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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pub tim15: TimClockSource,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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pub tim16: TimClockSource,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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pub tim17: TimClockSource,
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#[cfg(any(all(stm32f303, any(package_D, package_E))))]
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pub tim20: TimClockSource,
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}
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#[cfg(all(stm32f3, not(rcc_f37)))]
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impl Default for TimClockSources {
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fn default() -> Self {
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Self {
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tim1: TimClockSource::PClk2,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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all(stm32f302, any(package_D, package_E)),
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stm32f398
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))]
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tim2: TimClockSource::PClk2,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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all(stm32f302, any(package_D, package_E)),
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stm32f398
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))]
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tim34: TimClockSource::PClk2,
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#[cfg(any(
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all(stm32f303, any(package_B, package_C, package_D, package_E)),
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stm32f358,
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stm32f398
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))]
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tim8: TimClockSource::PClk2,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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tim15: TimClockSource::PClk2,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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tim16: TimClockSource::PClk2,
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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tim17: TimClockSource::PClk2,
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#[cfg(any(all(stm32f303, any(package_D, package_E))))]
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tim20: TimClockSource::PClk2,
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}
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}
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}
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/// Clocks configutation
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#[non_exhaustive]
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pub struct Config {
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@ -209,8 +99,8 @@ pub struct Config {
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pub adc34: AdcClockSource,
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#[cfg(stm32f334)]
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pub hrtim: HrtimClockSource,
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#[cfg(all(stm32f3, not(rcc_f37)))]
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pub tim: TimClockSources,
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#[cfg(cfgr3)]
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pub cfgr3: crate::_generated::CFGR3,
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pub ls: super::LsConfig,
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}
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@ -240,8 +130,8 @@ impl Default for Config {
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adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
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#[cfg(stm32f334)]
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hrtim: HrtimClockSource::BusClk,
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#[cfg(all(stm32f3, not(rcc_f37)))]
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tim: Default::default(),
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#[cfg(cfgr3)]
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cfgr3: Default::default(),
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}
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}
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}
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@ -477,107 +367,8 @@ pub(crate) unsafe fn init(config: Config) {
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}
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};
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#[cfg(all(stm32f3, not(rcc_f37)))]
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match config.tim.tim1 {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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all(stm32f302, any(package_D, package_E)),
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stm32f398
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))]
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match config.tim.tim2 {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
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}
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};
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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all(stm32f302, any(package_D, package_E)),
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stm32f398
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))]
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match config.tim.tim34 {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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#[cfg(any(
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all(stm32f303, any(package_B, package_C, package_D, package_E)),
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stm32f358,
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stm32f398
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))]
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match config.tim.tim8 {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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match config.tim.tim15 {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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match config.tim.tim16 {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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};
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#[cfg(any(
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all(stm32f303, any(package_D, package_E)),
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stm32f301,
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stm32f318,
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all(stm32f302, any(package_6, package_8)),
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stm32f398
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))]
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match config.tim.tim17 {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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}
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#[cfg(any(all(stm32f303, any(package_D, package_E))))]
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match config.tim.tim20 {
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TimClockSource::PClk2 => {}
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TimClockSource::PllClk => {
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RCC.cfgr3()
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.modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
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}
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}
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#[cfg(cfgr3)]
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config.cfgr3.init();
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set_clocks!(
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hsi: hsi,
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@ -17,7 +17,9 @@ bind_interrupts!(struct Irqs {
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p = embassy_stm32::init(Default::default());
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let mut init_config = embassy_stm32::Config::default();
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init_config.rcc.cfgr3.usart1sw = Some(embassy_stm32::pac::rcc::vals::Usart1sw::HSI);
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let p = embassy_stm32::init(init_config);
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info!("Hello World!");
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let config = Config::default();
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