Dario Nieuwenhuis
5caa4ac51b
Merge pull request #4124 from mickem/allow_stm32_to_re_init_rcc
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Add function to allow re-init rcc config for stm32
2025-05-13 20:57:33 +00:00
Dario Nieuwenhuis
0591d60a79
stm32/otg: calculate TRDT using AHB freq instead of kernel freq.
2025-04-30 18:11:20 +02:00
Michael Medin
a94cc79b9b
removed unused import
2025-04-28 18:52:03 +02:00
Michael Medin
1d578f5a7e
function needs to be pub(crate)
2025-04-28 09:21:21 +02:00
Michael Medin
74cb84eb4e
Moved functions to rcc module (this is a bit awkward as we now have two init functions in rcc: rcc::initand rcc::init_rcc)
2025-04-28 09:14:56 +02:00
Dario Nieuwenhuis
7512c5f14e
stm32: update metapac, cleanup clocks a bit.
2025-04-18 20:32:15 +02:00
Steven Friedman
bbf2a641dd
remove Hz from log
2025-04-08 09:36:35 -04:00
Steven Friedman
3cb178e78e
Frequency display is now consistent
2025-04-08 09:17:54 -04:00
Dario Nieuwenhuis
068b3c90d4
Merge pull request #3922 from antonellocontini/f413-fix-i2s-pll-source-selection
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Fix I2S PLL source selection for F413/F423/F412
2025-04-06 21:58:26 +00:00
techmccat
ce578b62b8
stm32: run cargo fmt
2025-03-28 10:45:14 +01:00
techmccat
0621087f6f
stm32: allow using LSI/LSE as SYSCLK on g0/c0
2025-03-28 10:35:05 +01:00
Dario Nieuwenhuis
d41eeeae79
Remove Peripheral trait, rename PeripheralRef->Peri.
2025-03-27 15:18:06 +01:00
Timofei Korostelev
8c6fa83006
Added ADC support for STM32C0.
2025-03-20 01:58:44 +01:00
antonello.contini
0c1601651b
cargo fmt
2025-02-25 22:02:23 +01:00
antonello.contini
724e1a34e5
simpler configuration
2025-02-25 21:37:01 +01:00
antonello.contini
51085a5e94
let user set external i2s clock frequency
2025-02-25 21:21:23 +01:00
antonello.contini
f1c7e388e6
do not use pllsrc for i2s; added field for plli2ssrc selection
2025-02-25 19:59:57 +01:00
vinsynth
6ec72c0af0
set PLLI2SM and plli2s_src f423
2025-02-02 18:53:06 -05:00
vinsynth
ce04cf8340
set PLLI2S M and SRC for f4 chips which support it
2025-02-02 18:12:34 -05:00
Dario Nieuwenhuis
4e3d066251
Merge pull request #3779 from algesten/fix/f107-rcc
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Full RCC support for STM32F107
2025-01-24 09:13:45 +00:00
Martin Algesten
4743501172
Move PLL2/3 config to before PLL
2025-01-24 10:06:32 +01:00
Martin Algesten
3ba94c0ab3
Fix init order of set_prediv1src
2025-01-24 09:36:11 +01:00
Martin Algesten
c72d9ec859
Review fixes
2025-01-24 09:16:24 +01:00
Markus Kasten
5d26bca2e7
stm32/rcc: add HSISYS support for g0
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adds support to divide HSI clock, which allows running in low power mode on HSI
2025-01-17 12:07:43 +01:00
Martin Algesten
9a159a8db0
Full RCC support for STM32F107
2025-01-16 15:31:41 +01:00
elagil
eba8089601
chore: fix build
2025-01-03 18:18:00 +01:00
Fabian Wolter
4b31639dca
STM32F0 fix using HSI48 as SYSCLK on devices with CRS
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Fixes #3651
2024-12-14 23:32:08 +01:00
Marvin Drees
a0e056a629
Update STM32U5 OTG HS clock handling
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Signed-off-by: Marvin Drees <marvin.drees@9elements.com>
2024-12-10 13:10:06 +01:00
Dario Nieuwenhuis
0d5cd7d692
Merge pull request #3582 from itswenb/main
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fix: Add missing clock check
2024-11-27 09:50:34 +00:00
Bing Wen
09c9f64b8e
Add missing clock check
2024-11-27 17:44:03 +08:00
Ulf Lilleengen
8e25bc56f6
Merge pull request #3574 from itswenb/main
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feat: Add new feature to enable overclocking
2024-11-27 07:38:00 +00:00
Bing Wen
d0340ad297
Fix & Revert
2024-11-27 12:33:32 +08:00
Bing Wen
52ab015fac
Add new
2024-11-27 12:23:13 +08:00
Bing Wen
8eaa3c8fd3
Add new feature to enable overclocking
2024-11-26 12:46:20 +08:00
Christian Enderle
48fd80919a
rcc: enable lse for stm32u0
2024-11-22 10:37:12 +01:00
Christian Enderle
f598cae376
compute lse and lsi frequency for STM32L and STM32U0 series
2024-11-21 12:12:00 +01:00
Christian Enderle
e76473ae95
fixed hanging when lse_sysen disabled
2024-11-18 12:23:56 +01:00
Christian Enderle
e09e4e9612
Enable user to choose to pass lse clock to peripherals
2024-11-18 12:23:56 +01:00
Junfeng Liu
4d75c4ee51
Fix wrong unit
2024-11-12 10:36:44 +08:00
Christian Enderle
cf2424f5c2
RCC: add lsi and lse clock frequency for STM32U5
2024-11-07 14:16:10 +01:00
Christian Enderle
7231032f97
RCC: added msik for stm32u5
2024-11-07 13:32:07 +01:00
elagil
e69be0a23b
fix: STM32U5 RCC fields
2024-11-06 19:46:55 +01:00
Dario Nieuwenhuis
ee669ee5c5
Update nighlty, fix warnings.
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Fixes #2599
2024-10-14 00:11:16 +02:00
Kevin
85b7c8957c
Add presence check for OTG_HS peripheral on STM32H7R/S series
2024-09-22 01:11:32 +02:00
Kevin
6d9af8304c
Add USBPHYC clock configuration for H7RS series
2024-09-22 00:23:07 +02:00
Kevin
2f60d78ea3
Add OTG_HS support for STM32H7R/S
2024-09-22 00:23:07 +02:00
Alexandros Liarokapis
2b7e76efe9
Fix dma nvic issues on dual core lines
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This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup.
Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration.
This ensures that each core will only handle the interrupts of the DMA channels that it uses.
2024-08-17 16:54:41 +03:00
Dion Dokter
2a7fe16ceb
Improve shared data placement, require less atomic support and use unsafecell for the clocks
2024-08-05 11:18:16 +02:00
Dion Dokter
f6f312270f
fmt
2024-07-09 09:37:49 +02:00
Dion Dokter
203297b569
Make clocks repr C.
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Add shared data.
Modify freq functions to use shared data.
Modify examples to use new init/
2024-07-08 16:54:06 +02:00
