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Add presence check for OTG_HS peripheral on STM32H7R/S series

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This commit is contained in:
Kevin 2024-09-22 01:11:32 +02:00
parent 6d9af8304c
commit 85b7c8957c
2 changed files with 10 additions and 8 deletions
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4
embassy-stm32/build.rs
View File

@ -55,7 +55,7 @@ fn main() {
let mut singletons: Vec<String> = Vec::new();
for p in METADATA.peripherals {
if let Some(r) = &p.registers {
if r.kind == "adccommon" || r.kind == "sai" || r.kind == "ucpd" {
if r.kind == "adccommon" || r.kind == "sai" || r.kind == "ucpd" || r.kind == "otg" {
// TODO: should we emit this for all peripherals? if so, we will need a list of all
// possible peripherals across all chips, so that we can declare the configs
// (replacing the hard-coded list of `peri_*` cfgs below)
@ -111,6 +111,8 @@ fn main() {
"peri_sai4",
"peri_ucpd1",
"peri_ucpd2",
"peri_usb_otg_fs",
"peri_usb_otg_hs",
]);
cfgs.declare_all(&["mco", "mco1", "mco2"]);

14
embassy-stm32/src/rcc/h.rs
View File

@ -34,11 +34,10 @@ pub enum VoltageScale {
Scale2,
Scale3,
}
#[cfg(any(stm32h7rs))]
pub use crate::pac::{
pwr::vals::Vos as VoltageScale,
rcc::vals::{Usbphycsel, Usbrefcksel},
};
#[cfg(stm32h7rs)]
pub use crate::pac::pwr::vals::Vos as VoltageScale;
#[cfg(all(stm32h7rs, peri_usb_otg_hs))]
pub use crate::pac::rcc::vals::{Usbphycsel, Usbrefcksel};
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum HseMode {
@ -560,14 +559,14 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
#[cfg(stm32h7rs)]
#[cfg(all(stm32h7rs, peri_usb_otg_hs))]
let usb_refck = match config.mux.usbphycsel {
Usbphycsel::HSE => hse,
Usbphycsel::HSE_DIV_2 => hse.map(|hse_val| hse_val / 2u8),
Usbphycsel::PLL3_Q => pll3.q,
_ => None,
};
#[cfg(stm32h7rs)]
#[cfg(all(stm32h7rs, peri_usb_otg_hs))]
let usb_refck_sel = match usb_refck {
Some(clk_val) => match clk_val {
Hertz(16_000_000) => Usbrefcksel::MHZ16,
@ -618,6 +617,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre5(config.apb5_pre);
});
#[cfg(peri_usb_otg_hs)]
RCC.ahbperckselr().modify(|w| {
w.set_usbrefcksel(usb_refck_sel);
});