Dario Nieuwenhuis
a6a5d9913c
Merge branch 'main' into stm32l0-reset-rtc
2024-02-23 01:45:10 +01:00
Dario Nieuwenhuis
0665e0d452
stm32/rcc: port U5 to new API, add all PLLs, all HSE modes.
2024-02-23 01:24:05 +01:00
Dario Nieuwenhuis
4481c5f3cc
Merge pull request #2616 from embassy-rs/h5-stupid-errata
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stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.
2024-02-23 00:25:30 +01:00
Dario Nieuwenhuis
475dea0208
stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.
2024-02-23 00:18:24 +01:00
Dario Nieuwenhuis
9c918f6474
Merge pull request #2588 from cschuhen/feature/fdcan_buffered
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Add FDCAN Buffered mode.
2024-02-23 00:07:05 +01:00
Torin Cooper-Bennun
5d2ccc8fa7
adc: basic H5 support
2024-02-22 15:50:13 +00:00
Eli Orona
88e29608ed
Rust fmt
2024-02-20 17:59:51 -08:00
Eli Orona
2ee9b37373
Move to a single Mux Struct.
2024-02-20 17:54:35 -08:00
Joonas Javanainen
9b2d096f4f
USB needs PWR_CR2 USV set on STM32L4
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Confirmed to be needed on an STM32L422, and based on a quick look at
L4/L4+ reference manuals, this bit is present and required to be set on
all L4 chips that have some kind of USB peripheral (USB or OTG_FS).
The `usb_otg` driver already sets it for `cfg(stm32l4)` and we should do
the same thing here.
2024-02-20 21:47:13 +02:00
Dario Nieuwenhuis
55187c7276
Merge pull request #2602 from embassy-rs/peripheralref-no-derefmut
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hal-internal: remove impl DerefMut for PeripheralRef.
2024-02-20 13:51:01 +00:00
Dario Nieuwenhuis
e8474426d8
hal-internal: remove impl DerefMut for PeripheralRef.
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if you have `PeripheralRef<'a, AnyPIn>` for pin A, and `AnyPin` (owned) for pin B, you can `mem::swap` them.
so, getting access forever to pin A, just by "sacrificing" pin B
this defeats the point of PeripheralRef, which is if you got a `PeripheralRef<'a, T>` then you're only allowed to use the peripheral for `'a`.
Also some drivers rely on the fact only one instance of a singleton exists for soundness, so this is a soundness fix for those.
2024-02-20 01:02:15 +01:00
Torin Cooper-Bennun
67230dc444
flash: h50: first pass at implementation
2024-02-19 16:05:50 +00:00
fe1es
5b7e2d8826
stm32/rcc: reset RTC on stm32l0
2024-02-19 15:25:24 +09:00
Corey Schuhen
eafa90cd07
Remove the OperatingMode typestates
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Instead have two explcit types(without the mode generic arg)types:
- One for config
- One for all operating modes
2024-02-18 13:09:37 +10:00
Zach
dd9f0d9d9e
support u5 flash
2024-02-17 12:04:53 -06:00
Corey Schuhen
5ad291b708
Add a buffered mode.
2024-02-17 18:26:57 +10:00
Corey Schuhen
91c75c92a0
Clean up and prep for buffered IRQ mode.
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- Reduce code duplicaiton in read/write methods
- General clean-up
- Prepare for buffered mode
2024-02-17 18:26:57 +10:00
Corey Schuhen
5d8c54fdea
Move error conversion to peripheral.rs
2024-02-17 18:25:58 +10:00
Corey Schuhen
200ace566f
Don't use word Standard for frame format because it can be confused with ID format. Use Classic instead to mean CAN 2.0B frames.
2024-02-17 18:25:58 +10:00
Corey Schuhen
70b3c4374d
Port FDCAN HAL to use PAC directly instead of fdcan crate.
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- Provide separate FDCAN capable and Classic CAN API's
- Don't use fdcan crate dep anymore
- Provide embedded-can traits.
2024-02-17 18:25:58 +10:00
Eli Orona
e99ef49611
Move to auto-generated based system.
2024-02-16 19:57:00 -08:00
Dario Nieuwenhuis
a3f508e6d1
Merge pull request #2570 from eZioPan/time-driver-singleton
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Add missing TIM for time-driver; reorder time-driver selection when use "time-drvier-any"
2024-02-17 02:34:45 +00:00
Eli Orona
c99c4a01a9
Update f013.rs
2024-02-16 16:47:38 -08:00
Eli Orona
7592e8be6e
Fix build
2024-02-16 16:45:58 -08:00
Eli Orona
77739faaeb
Rustfmt
2024-02-16 16:42:19 -08:00
Eli Orona
370db9fb06
Update f013.rs
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Add stm32f398
2024-02-16 16:39:23 -08:00
Dario Nieuwenhuis
9352621058
Merge pull request #2579 from barnabywalters/g4rcc
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[embassy-stm32]: stm32g4 RCC refactor
2024-02-16 23:38:49 +00:00
Barnaby Walters
6d7458dac7
Refinements
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* Implemented boost mode dance (RM0440 p234-245, 6.5.1)
* Enabled boost mode in usb_serial example, tested on hardware
* Removed hard requirement of a valid 48MHz source (HSI48 is checked if
requested, PLL passed through as-is and assumed to be valid)
* Used calc_pclk to calculate APB frequencies
* Refactored 48MHz configuration code to remove unnecessary let and block
* Renamed ahb_freq to hclk for clarity and consistency
2024-02-17 00:30:16 +01:00
Barnaby Walters
a24087c36c
Configured SYSCLK after boost mode, added comments
2024-02-16 21:52:58 +01:00
Barnaby Walters
e465dacf73
Added documentation, fixed and refined boost and flash read latency config
2024-02-16 21:34:12 +01:00
Barnaby Walters
25a95503f6
Configured HSI48 if enabled, assert is enabled if chosen as clk48 source
2024-02-16 20:41:04 +01:00
Barnaby Walters
ae74833999
Removed redundant HSI48 configuration
2024-02-16 20:32:35 +01:00
Barnaby Walters
32e4c93954
Removed dangling doc comments
2024-02-16 19:58:19 +01:00
Eli Orona
d7623c7929
Remove extraneous , in cfg
2024-02-15 23:20:35 -08:00
Eli Orona
d28ba1d606
rustfmt
2024-02-15 23:16:17 -08:00
Eli Orona
56b345c722
Clean up register setting
2024-02-15 23:12:18 -08:00
Eli Orona
4408c169a5
Fix cfg lines
2024-02-15 22:55:11 -08:00
Eli Orona
029d6383b5
Rust fmt and fix build.
2024-02-15 20:02:25 -08:00
Eli Orona
169f1ce928
I believe that this enables the PLL clock input to different TIMs for the STM32F3xx Series of chips.
2024-02-15 19:50:42 -08:00
Dario Nieuwenhuis
ae02467434
stm32: update metapac.
2024-02-16 02:07:21 +01:00
Barnaby Walters
396041ad1a
Commented out currently unused constants
2024-02-16 00:04:35 +01:00
Barnaby Walters
5b7eff6541
[embassy-stm32]: started stm32g4 RCC refactor
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* Copied API from f.rs where applicable
* HSE and HSI independantly configurable
* Boost mode set by user rather
* Added HSE, pll1_q and pll1_p frequencies to set_clocks call
* Stubbed max module based on f.rs, needs cleanup
2024-02-15 23:56:26 +01:00
Dario Nieuwenhuis
5220453d85
Merge pull request #2564 from embassy-rs/rcc-f1-update
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stm32/rcc: port F1, F0 to new API.
2024-02-14 16:40:11 +00:00
Dario Nieuwenhuis
1860e22693
stm32/rcc: unify f0, f1, f3.
2024-02-14 17:24:20 +01:00
eZio Pan
bbe1eebc53
Add missing TIM for time-driver; reorder time-driver selection when use "time-drvier-any".
2024-02-14 17:43:46 +08:00
Michael de Silva
0ceb313b6f
FIX: Correct typo in stm32 gpio
2024-02-14 07:22:52 +05:30
Caleb Garrett
14a678fe45
Fixed HMAC blocking mode.
2024-02-12 20:33:04 -05:00
Caleb Garrett
d8b4922b3c
Add STM32 HMAC function.
2024-02-12 20:33:04 -05:00
Dario Nieuwenhuis
8c82d1bcbc
Merge pull request #2528 from caleb-garrett/hash
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STM32 Hash Accelerator
2024-02-13 01:36:11 +01:00
Dario Nieuwenhuis
ccd2c574c3
stm32/rcc: port F0 to new API.
2024-02-13 01:21:51 +01:00
