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Merge pull request #4231 from ROMemories/feat/stm32-rcc-const-constructors

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feat(stm32): provide a `const` constructor on `rcc::Config`
This commit is contained in:
Dario Nieuwenhuis 2025-06-01 12:19:39 +00:00 committed by GitHub
commit f3983328e0
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GPG Key ID: B5690EEEBB952194
11 changed files with 115 additions and 55 deletions
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19
embassy-stm32/src/rcc/bd.rs
View File

@ -92,6 +92,17 @@ pub struct LsConfig {
}
impl LsConfig {
/// Creates an [`LsConfig`] using the LSI when possible.
pub const fn new() -> Self {
// on L5, just the fact that LSI is enabled makes things crash.
// TODO: investigate.
#[cfg(not(stm32l5))]
return Self::default_lsi();
#[cfg(stm32l5)]
return Self::off();
}
pub const fn default_lse() -> Self {
Self {
rtc: RtcClockSource::LSE,
@ -124,13 +135,7 @@ impl LsConfig {
impl Default for LsConfig {
fn default() -> Self {
// on L5, just the fact that LSI is enabled makes things crash.
// TODO: investigate.
#[cfg(not(stm32l5))]
return Self::default_lsi();
#[cfg(stm32l5)]
return Self::off();
Self::new()
}
}

15
embassy-stm32/src/rcc/c0.rs
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@ -59,9 +59,8 @@ pub struct Config {
pub mux: super::mux::ClockMux,
}
impl Default for Config {
#[inline]
fn default() -> Config {
impl Config {
pub const fn new() -> Self {
Config {
hsi: Some(Hsi {
sys_div: HsiSysDiv::DIV4,
@ -71,12 +70,18 @@ impl Default for Config {
sys: Sysclk::HSISYS,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
ls: Default::default(),
mux: Default::default(),
ls: crate::rcc::LsConfig::new(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Config {
Self::new()
}
}
pub(crate) unsafe fn init(config: Config) {
// Turn on the HSI
match config.hsi {

16
embassy-stm32/src/rcc/f013.rs
View File

@ -126,13 +126,13 @@ pub struct Config {
pub ls: super::LsConfig,
}
impl Default for Config {
fn default() -> Self {
impl Config {
pub const fn new() -> Self {
Self {
hsi: true,
hse: None,
#[cfg(crs)]
hsi48: Some(Default::default()),
hsi48: Some(crate::rcc::Hsi48Config::new()),
sys: Sysclk::HSI,
pll: None,
@ -147,7 +147,7 @@ impl Default for Config {
apb1_pre: APBPrescaler::DIV1,
#[cfg(not(stm32f0))]
apb2_pre: APBPrescaler::DIV1,
ls: Default::default(),
ls: crate::rcc::LsConfig::new(),
#[cfg(stm32f1)]
// ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
@ -163,11 +163,17 @@ impl Default for Config {
#[cfg(stm32f107)]
i2s3_src: I2s2src::SYS,
mux: Default::default(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Self {
Self::new()
}
}
/// Initialize and Set the clock frequencies
pub(crate) unsafe fn init(config: Config) {
// Turn on the HSI

14
embassy-stm32/src/rcc/f247.rs
View File

@ -108,8 +108,8 @@ pub struct Config {
pub voltage: VoltageScale,
}
impl Default for Config {
fn default() -> Self {
impl Config {
pub const fn new() -> Self {
Self {
hsi: true,
hse: None,
@ -127,15 +127,21 @@ impl Default for Config {
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
ls: Default::default(),
ls: crate::rcc::LsConfig::new(),
#[cfg(stm32f2)]
voltage: VoltageScale::Range3,
mux: Default::default(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Self {
Self::new()
}
}
pub(crate) unsafe fn init(config: Config) {
// set VOS to SCALE1, if use PLL
// TODO: check real clock speed before set VOS

17
embassy-stm32/src/rcc/g0.rs
View File

@ -97,9 +97,8 @@ pub struct Config {
pub mux: super::mux::ClockMux,
}
impl Default for Config {
#[inline]
fn default() -> Config {
impl Config {
pub const fn new() -> Self {
Config {
hsi: Some(Hsi {
sys_div: HsiSysDiv::DIV1,
@ -107,18 +106,24 @@ impl Default for Config {
hse: None,
sys: Sysclk::HSI,
#[cfg(crs)]
hsi48: Some(Default::default()),
hsi48: Some(crate::rcc::Hsi48Config::new()),
pll: None,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
low_power_run: false,
ls: Default::default(),
ls: crate::rcc::LsConfig::new(),
voltage_range: VoltageRange::RANGE1,
mux: Default::default(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Config {
Self::new()
}
}
#[derive(Default)]
pub struct PllFreq {
pub pll_p: Option<Hertz>,

17
embassy-stm32/src/rcc/g4.rs
View File

@ -91,26 +91,31 @@ pub struct Config {
pub mux: super::mux::ClockMux,
}
impl Default for Config {
#[inline]
fn default() -> Config {
impl Config {
pub const fn new() -> Self {
Config {
hsi: true,
hse: None,
sys: Sysclk::HSI,
hsi48: Some(Default::default()),
hsi48: Some(crate::rcc::Hsi48Config::new()),
pll: None,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
low_power_run: false,
ls: Default::default(),
ls: crate::rcc::LsConfig::new(),
boost: false,
mux: Default::default(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Config {
Self::new()
}
}
#[derive(Default)]
pub struct PllFreq {
pub pll_p: Option<Hertz>,

16
embassy-stm32/src/rcc/h.rs
View File

@ -218,13 +218,13 @@ pub struct Config {
pub mux: super::mux::ClockMux,
}
impl Default for Config {
fn default() -> Self {
impl Config {
pub const fn new() -> Self {
Self {
hsi: Some(HSIPrescaler::DIV1),
hse: None,
csi: false,
hsi48: Some(Default::default()),
hsi48: Some(crate::rcc::Hsi48Config::new()),
sys: Sysclk::HSI,
pll1: None,
pll2: None,
@ -248,16 +248,22 @@ impl Default for Config {
voltage_scale: VoltageScale::Scale0,
#[cfg(rcc_h7rs)]
voltage_scale: VoltageScale::HIGH,
ls: Default::default(),
ls: crate::rcc::LsConfig::new(),
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468, pwr_h7rs))]
supply_config: SupplyConfig::LDO,
mux: Default::default(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Self {
Self::new()
}
}
pub(crate) unsafe fn init(config: Config) {
#[cfg(any(stm32h7))]
let pwr_reg = PWR.cr3();

8
embassy-stm32/src/rcc/hsi48.rs
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@ -18,9 +18,15 @@ pub struct Hsi48Config {
pub sync_from_usb: bool,
}
impl Hsi48Config {
pub const fn new() -> Self {
Self { sync_from_usb: false }
}
}
impl Default for Hsi48Config {
fn default() -> Self {
Self { sync_from_usb: false }
Self::new()
}
}

17
embassy-stm32/src/rcc/l.rs
View File

@ -68,9 +68,8 @@ pub struct Config {
pub mux: super::mux::ClockMux,
}
impl Default for Config {
#[inline]
fn default() -> Config {
impl Config {
pub const fn new() -> Self {
Config {
hse: None,
hsi: false,
@ -90,15 +89,21 @@ impl Default for Config {
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
pllsai2: None,
#[cfg(crs)]
hsi48: Some(Default::default()),
ls: Default::default(),
hsi48: Some(crate::rcc::Hsi48Config::new()),
ls: crate::rcc::LsConfig::new(),
#[cfg(any(stm32l0, stm32l1))]
voltage_scale: VoltageScale::RANGE1,
mux: Default::default(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Config {
Self::new()
}
}
#[cfg(stm32wb)]
pub const WPAN_DEFAULT: Config = Config {
hse: Some(Hse {

16
embassy-stm32/src/rcc/u5.rs
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@ -97,14 +97,14 @@ pub struct Config {
pub mux: super::mux::ClockMux,
}
impl Default for Config {
fn default() -> Self {
impl Config {
pub const fn new() -> Self {
Self {
msis: Some(Msirange::RANGE_4MHZ),
msik: Some(Msirange::RANGE_4MHZ),
hse: None,
hsi: false,
hsi48: Some(Default::default()),
hsi48: Some(crate::rcc::Hsi48Config::new()),
pll1: None,
pll2: None,
pll3: None,
@ -114,12 +114,18 @@ impl Default for Config {
apb2_pre: APBPrescaler::DIV1,
apb3_pre: APBPrescaler::DIV1,
voltage_range: VoltageScale::RANGE1,
ls: Default::default(),
mux: Default::default(),
ls: crate::rcc::LsConfig::new(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Self {
Self::new()
}
}
pub(crate) unsafe fn init(config: Config) {
// Set the requested power mode
PWR.vosr().modify(|w| w.set_vos(config.voltage_range));

15
embassy-stm32/src/rcc/wba.rs
View File

@ -37,9 +37,8 @@ pub struct Config {
pub mux: super::mux::ClockMux,
}
impl Default for Config {
#[inline]
fn default() -> Config {
impl Config {
pub const fn new() -> Self {
Config {
hse: None,
hsi: true,
@ -48,13 +47,19 @@ impl Default for Config {
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
apb7_pre: APBPrescaler::DIV1,
ls: Default::default(),
ls: crate::rcc::LsConfig::new(),
voltage_scale: VoltageScale::RANGE2,
mux: Default::default(),
mux: super::mux::ClockMux::default(),
}
}
}
impl Default for Config {
fn default() -> Config {
Self::new()
}
}
fn hsi_enable() {
RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}