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fix: STM32F4 I2S clock calculations

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This commit is contained in:
elagil 2025-01-03 22:57:31 +01:00
parent e68efc2d7c
commit cf606a161f
2 changed files with 14 additions and 4 deletions
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10
embassy-stm32/build.rs
View File

@ -712,6 +712,16 @@ fn main() {
// Generate RCC
clock_gen.clock_names.insert("sys".to_string());
clock_gen.clock_names.insert("rtc".to_string());
// STM32F4 SPI in I2S mode receives a clock input from the dedicated I2S PLL.
// For this, there is an additional clock MUX, which is not present in other
// peripherals and does not fit the current RCC structure of stm32-data.
if chip_name.starts_with("stm32f4") && !chip_name.starts_with("stm32f410") {
clock_gen.clock_names.insert("plli2s1_p".to_string());
clock_gen.clock_names.insert("plli2s1_q".to_string());
clock_gen.clock_names.insert("plli2s1_r".to_string());
}
let clock_idents: Vec<_> = clock_gen.clock_names.iter().map(|n| format_ident!("{}", n)).collect();
g.extend(quote! {
#[derive(Clone, Copy, Debug)]

8
embassy-stm32/src/i2s.rs
View File

@ -7,6 +7,7 @@ use stm32_metapac::spi::vals;
use crate::dma::{ringbuffer, ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
use crate::mode::Async;
use crate::rcc::get_freqs;
use crate::spi::{Config as SpiConfig, RegsExt as _, *};
use crate::time::Hertz;
use crate::{Peripheral, PeripheralRef};
@ -491,10 +492,9 @@ impl<'d, W: Word> I2S<'d, W> {
let regs = T::info().regs;
// TODO move i2s to the new mux infra.
//#[cfg(all(rcc_f4, not(stm32f410)))]
//let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
//#[cfg(stm32f410)]
#[cfg(all(rcc_f4, not(stm32f410)))]
let pclk = unsafe { get_freqs() }.plli2s1_r.to_hertz().unwrap();
#[cfg(stm32f410)]
let pclk = T::frequency();
let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);