From cf606a161f9bed59f912f3e521bc48a8cda11d6f Mon Sep 17 00:00:00 2001
From: elagil <elagil@takanome.de>
Date: Fri, 3 Jan 2025 22:57:31 +0100
Subject: [PATCH] fix: STM32F4 I2S clock calculations

---
 embassy-stm32/build.rs   | 10 ++++++++++
 embassy-stm32/src/i2s.rs |  8 ++++----
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index e293cf965..a70524916 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -712,6 +712,16 @@ fn main() {
     // Generate RCC
     clock_gen.clock_names.insert("sys".to_string());
     clock_gen.clock_names.insert("rtc".to_string());
+
+    // STM32F4 SPI in I2S mode receives a clock input from the dedicated I2S PLL.
+    // For this, there is an additional clock MUX, which is not present in other
+    // peripherals and does not fit the current RCC structure of stm32-data.
+    if chip_name.starts_with("stm32f4") && !chip_name.starts_with("stm32f410") {
+        clock_gen.clock_names.insert("plli2s1_p".to_string());
+        clock_gen.clock_names.insert("plli2s1_q".to_string());
+        clock_gen.clock_names.insert("plli2s1_r".to_string());
+    }
+
     let clock_idents: Vec<_> = clock_gen.clock_names.iter().map(|n| format_ident!("{}", n)).collect();
     g.extend(quote! {
         #[derive(Clone, Copy, Debug)]
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index 79d6279f6..1a7393ba4 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -7,6 +7,7 @@ use stm32_metapac::spi::vals;
 use crate::dma::{ringbuffer, ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
 use crate::mode::Async;
+use crate::rcc::get_freqs;
 use crate::spi::{Config as SpiConfig, RegsExt as _, *};
 use crate::time::Hertz;
 use crate::{Peripheral, PeripheralRef};
@@ -491,10 +492,9 @@ impl<'d, W: Word> I2S<'d, W> {
 
         let regs = T::info().regs;
 
-        // TODO move i2s to the new mux infra.
-        //#[cfg(all(rcc_f4, not(stm32f410)))]
-        //let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
-        //#[cfg(stm32f410)]
+        #[cfg(all(rcc_f4, not(stm32f410)))]
+        let pclk = unsafe { get_freqs() }.plli2s1_r.to_hertz().unwrap();
+        #[cfg(stm32f410)]
         let pclk = T::frequency();
 
         let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);