fix formatting

This commit is contained in:
klownfish 2024-12-31 01:04:18 +01:00
parent a5a90156ce
commit 41c8bf867b
4 changed files with 30 additions and 47 deletions

View File

@ -259,4 +259,4 @@ pub const fn resolution_to_max_count(res: Resolution) -> u32 {
#[allow(unreachable_patterns)] #[allow(unreachable_patterns)]
_ => core::unreachable!(), _ => core::unreachable!(),
} }
} }

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@ -1,17 +1,12 @@
pub use crate::pac::adc::vals::Adc4Res as Resolution;
pub use crate::pac::adc::vals::Adc4SampleTime as SampleTime;
pub use crate::pac::adc::vals::Adc4Presc as Presc;
pub use crate::pac::adc::regs::Adc4Chselrmod0;
#[allow(unused)] #[allow(unused)]
use pac::adc::vals::{Adc4Exten, Adc4OversamplingRatio, Adc4Dmacfg}; use pac::adc::vals::{Adc4Dmacfg, Adc4Exten, Adc4OversamplingRatio};
use super::{ use super::{blocking_delay_us, AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel};
blocking_delay_us, AdcChannel, SealedAdcChannel, AnyAdcChannel, RxDma4 use crate::dma::Transfer;
}; pub use crate::pac::adc::regs::Adc4Chselrmod0;
pub use crate::pac::adc::vals::{Adc4Presc as Presc, Adc4Res as Resolution, Adc4SampleTime as SampleTime};
use crate::time::Hertz; use crate::time::Hertz;
use crate::{pac, rcc, Peripheral}; use crate::{pac, rcc, Peripheral};
use crate::dma::Transfer;
const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55); const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
@ -74,7 +69,7 @@ impl<T: Instance> SealedAdcChannel<T> for Vcore {
pub enum DacChannel { pub enum DacChannel {
OUT1, OUT1,
OUT2 OUT2,
} }
/// Number of samples used for averaging. /// Number of samples used for averaging.
@ -186,7 +181,7 @@ pub struct Adc4<'d, T: Instance> {
#[derive(Debug)] #[derive(Debug)]
pub enum Adc4Error { pub enum Adc4Error {
InvalidSequence, InvalidSequence,
DMAError DMAError,
} }
impl<'d, T: Instance> Adc4<'d, T> { impl<'d, T: Instance> Adc4<'d, T> {
@ -205,9 +200,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
panic!("Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 / 1_000_000 ); panic!("Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 / 1_000_000 );
} }
let mut s = Self { let mut s = Self { adc };
adc,
};
s.power_up(); s.power_up();
@ -227,7 +220,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
T::regs().cr().modify(|w| { T::regs().cr().modify(|w| {
w.set_advregen(true); w.set_advregen(true);
}); });
while !T::regs().isr().read().ldordy() { }; while !T::regs().isr().read().ldordy() {}
T::regs().isr().modify(|w| { T::regs().isr().modify(|w| {
w.set_ldordy(true); w.set_ldordy(true);
@ -300,8 +293,8 @@ impl<'d, T: Instance> Adc4<'d, T> {
pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac { pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
let mux; let mux;
match dac { match dac {
DacChannel::OUT1 => {mux = false}, DacChannel::OUT1 => mux = false,
DacChannel::OUT2 => {mux = true} DacChannel::OUT2 => mux = true,
} }
T::regs().or().modify(|w| w.set_chn21sel(mux)); T::regs().or().modify(|w| w.set_chn21sel(mux));
Dac {} Dac {}
@ -346,7 +339,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
} }
/// Read an ADC channel. /// Read an ADC channel.
pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16{ pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
channel.setup(); channel.setup();
// Select channel // Select channel
@ -440,7 +433,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
T::regs().chselrmod0().modify(|w| { T::regs().chselrmod0().modify(|w| {
w.set_chsel(channel.channel as usize, true); w.set_chsel(channel.channel as usize, true);
}); });
}; }
let request = rx_dma.request(); let request = rx_dma.request();
let transfer = unsafe { let transfer = unsafe {
@ -483,4 +476,4 @@ impl<'d, T: Instance> Adc4<'d, T> {
while T::regs().cr().read().adstart() {} while T::regs().cr().read().adstart() {}
} }
} }
} }

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@ -1,9 +1,7 @@
#[allow(unused)]
use pac::adc::vals::{Adstp, Difsel, Exten, Pcsel, Dmngt};
#[cfg(not(stm32u5))] #[cfg(not(stm32u5))]
use pac::adc::vals::{Adcaldif, Boost}; use pac::adc::vals::{Adcaldif, Boost};
#[allow(unused)]
use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
use pac::adccommon::vals::Presc; use pac::adccommon::vals::Presc;
use super::{ use super::{
@ -26,7 +24,6 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
#[cfg(stm32u5)] #[cfg(stm32u5)]
const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55); const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
#[cfg(stm32g4)] #[cfg(stm32g4)]
const VREF_CHANNEL: u8 = 18; const VREF_CHANNEL: u8 = 18;
#[cfg(stm32g4)] #[cfg(stm32g4)]
@ -41,7 +38,6 @@ const TEMP_CHANNEL: u8 = 18;
#[cfg(not(stm32u5))] #[cfg(not(stm32u5))]
const VBAT_CHANNEL: u8 = 17; const VBAT_CHANNEL: u8 = 17;
#[cfg(stm32u5)] #[cfg(stm32u5)]
const VREF_CHANNEL: u8 = 0; const VREF_CHANNEL: u8 = 0;
#[cfg(stm32u5)] #[cfg(stm32u5)]

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@ -1,19 +1,14 @@
#![no_std] #![no_std]
#![no_main] #![no_main]
use defmt::*;
use defmt::{*};
use defmt_rtt as _;
use embassy_stm32::adc; use embassy_stm32::adc;
use embassy_stm32::adc::AdcChannel; use embassy_stm32::adc::{adc4, AdcChannel};
use embassy_stm32::adc::adc4; use {defmt_rtt as _, panic_probe as _};
use panic_probe as _;
#[embassy_executor::main] #[embassy_executor::main]
async fn main(spawner: embassy_executor::Spawner) { async fn main(_spawner: embassy_executor::Spawner) {
let mut config = embassy_stm32::Config::default(); let config = embassy_stm32::Config::default();
let mut p = embassy_stm32::init(config); let mut p = embassy_stm32::init(config);
@ -84,7 +79,8 @@ async fn main(spawner: embassy_executor::Spawner) {
] ]
.into_iter(), .into_iter(),
&mut measurements, &mut measurements,
).await; )
.await;
let volt1: f32 = 3.3 * measurements[0] as f32 / max1 as f32; let volt1: f32 = 3.3 * measurements[0] as f32 / max1 as f32;
let volt2: f32 = 3.3 * measurements[1] as f32 / max1 as f32; let volt2: f32 = 3.3 * measurements[1] as f32 / max1 as f32;
@ -101,15 +97,13 @@ async fn main(spawner: embassy_executor::Spawner) {
// The channels must be in ascending order and can't repeat for ADC4 // The channels must be in ascending order and can't repeat for ADC4
adc4.read( adc4.read(
&mut p.GPDMA1_CH1, &mut p.GPDMA1_CH1,
[ [&mut degraded42, &mut degraded41].into_iter(),
&mut degraded42,
&mut degraded41,
]
.into_iter(),
&mut measurements, &mut measurements,
).await.unwrap(); )
.await
.unwrap();
let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32; let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
let volt1: f32 = 3.3 * measurements[1] as f32 / max4 as f32; let volt1: f32 = 3.3 * measurements[1] as f32 / max4 as f32;
info!("Async read 4 pin 1 {}", volt1); info!("Async read 4 pin 1 {}", volt1);
info!("Async read 4 pin 2 {}", volt2); info!("Async read 4 pin 2 {}", volt2);
} }