Tweaks to Huvud 0.6x

This commit is contained in:
Pontus Borg
2021-05-04 22:16:19 +02:00
parent 2d90078e6b
commit 017b953e9a
3 changed files with 1392 additions and 1668 deletions

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@@ -1,4 +1,4 @@
update=29/10/2020 17:47:46
update=22/04/2021 21:31:31
version=1
last_client=kicad
[general]
@@ -12,6 +12,16 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@@ -24,10 +34,10 @@ RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
MinHoleToHole=0.2
TrackWidth1=0.2
TrackWidth2=0.2
TrackWidth3=0.25
@@ -37,8 +47,10 @@ TrackWidth6=0.4
TrackWidth7=0.8
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter2=0.4
ViaDrill2=0.2
ViaDiameter3=0.6
ViaDrill3=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
@@ -235,7 +247,7 @@ Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.127
Clearance=0.09
TrackWidth=0.2
ViaDiameter=0.8
ViaDrill=0.4
@@ -266,13 +278,3 @@ uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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