24 Commits

Author SHA1 Message Date
17d6f752e5
add 3d model 2025-06-05 13:58:57 +02:00
343e1da505
last touches and add exports 2025-06-03 18:06:06 +02:00
232815e7e5
is the fist prototype done? 2025-05-27 15:04:34 +02:00
c9c2408ffc
almost done 2025-05-26 15:24:51 +02:00
29dedb9b7c
wow, there are more connections done 2025-05-23 16:04:44 +02:00
e11417f1ed
even more shit is done now 2025-05-23 15:20:15 +02:00
64d8f8c61d
make some more connections 2025-05-23 12:10:16 +02:00
4f4dd60970
a bit more DRC 2025-05-22 13:03:19 +02:00
42a9051e58
start with the power planes 2025-05-21 13:53:47 +02:00
f7dd37a855
some edits 2025-05-20 16:43:39 +02:00
a889dbb949
fix merge and redo pcb layout 2025-05-20 14:58:41 +02:00
fc764d61c2
Merge commit '948fcb827c361b22ffa39dbd876c94d9b7aaaa4d' 2025-05-20 12:27:49 +02:00
f5f5e8316d
add more components info 2025-05-20 12:20:49 +02:00
948fcb827c
start with pcb layout 2025-05-19 23:47:41 +02:00
67cf8ce4db
add info to components 2025-05-16 14:39:28 +02:00
2f8fb0ca89
almost ready 2025-05-16 13:25:31 +02:00
7ddd443c31
update bom 2025-05-15 13:09:11 +02:00
e30ee5671a
add digikey part numbers 2025-05-08 14:48:05 +02:00
6ef70dc60f
simulate in ltspice 2025-05-06 17:18:35 +02:00
a55e21c4a8
was very close with a working simulation 2025-05-01 00:06:01 +02:00
656cd8c217
more connections 2025-04-24 15:41:16 +02:00
5df5986392
add rp2040 2025-04-24 13:08:52 +02:00
0802754636
setup for simulation 2025-04-23 12:17:36 +02:00
9b9627597f
first half bridge driver 2025-04-21 19:25:35 +02:00