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699cd62939
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83c27b43dd |
1
.gitignore
vendored
1
.gitignore
vendored
@ -11,4 +11,5 @@
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/.cproject
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/.ccsproject
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/.project
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/.launches
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/lnk_*.cmd
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@ -8,6 +8,7 @@
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Lightly modified by Mats van Reenen: use other SPI interface
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*/
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#include <msp430.h>
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#include <Mfrc522.h>
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#include <SPI.h>
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//#include <SPI2.h>
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1
NFC.c
1
NFC.c
@ -1,5 +1,4 @@
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#include <msp430.h>
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#include "NFC.h"
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#include "SPI2.h"
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#include "Mfrc522.h"
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2
SPI.c
2
SPI.c
@ -78,7 +78,7 @@ void SPISend(){
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while(UCB0STAT & UCBUSY); // wait for SPI TX/RX to finish
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// save recieved data
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SPI_packet[SPI_packetC] = UCA0RXIFG;
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SPI_packet[SPI_packetC] = UCA0RXBUF;
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// increase counter for next byte
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SPI_packetC++;
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2
SPI.h
2
SPI.h
@ -10,7 +10,7 @@
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#include "typedefExtention.h"
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enum SPI_Mode {SPI_Mode0=0b00<<6, SPI_Mode1=0b10<<6, SPI_Mode2=0b11<<6, SPI_Mode3=0b01<<6};
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enum SPI_Mode {SPI_Mode0=0b10<<6, SPI_Mode1=0b00<<6, SPI_Mode2=0b11<<6, SPI_Mode3=0b01<<6};
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enum SPI_Clock {SPI_Clock_1MHz=16, SPI_Clock_2MHz=8, SPI_Clock_4MHz=4, SPI_Clock_8MHz=2};
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uchar SPI_packet[5];
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4
main.c
4
main.c
@ -41,8 +41,6 @@
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*/
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int main(void)
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{
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int v;
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WDTCTL = WDTPW | WDTHOLD; // stop watchdog timer
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// set cpu op 16MHz
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@ -52,7 +50,7 @@ int main(void)
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SPIInit();
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MDInit();
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MCInit();
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NFCInit();
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//NFCInit();
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return 0;
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}
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@ -6,40 +6,52 @@
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*/
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#include <msp430.h>
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#include "typedefExtention.h"
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#include "SPI.h"
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#include "motorDriver.h"
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const uchar MD_CS = BIT3;
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// register 0x00 GCINF
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#define MD_GCONF 0X00
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#define MD_GCONF_singgelMotor 0x00000001
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#define MD_GCONF_stepdir1Enable 0x00000002
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#define MD_GCONF_stepdir2Enable 0x00000004
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#define MD_GCONF_motor1Revers 0x00000010
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#define MD_GCONF_motor1Revers 0x00000010
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#define MD_GCONF_lockGCONF 0x00000020
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#define MD_GCONF 0x00
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#define MD_GCONF_singgelMotor BIT00
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#define MD_GCONF_stepdir1Enable BIT01
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#define MD_GCONF_stepdir2Enable BIT02
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#define MD_GCONF_motor1Revers BIT08
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#define MD_GCONF_motor2Revers BIT09
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#define MD_GCONF_lockGCONF BIT10
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// register 0x01 GSTAT
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#define MD_GSTAT 0X01
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#define MD_GSTAT 0x01
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#define MD_GSTAT_recet BIT00
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#define MD_GSTAT_drv_err1 BIT01
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#define MD_GSTAT_drv_err2 BIT02
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#define MD_GSTAT_un_cp BIT03
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// register 0x30, 0x50 IHOLD_IRUN
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#define MD_IHIR1 0x30
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#define MD_IHIR2 0x50
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#define MD_IHIR_iHold 0
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#define MD_IHIR_iRun 8
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#define md_IHIR_iHoldDelay 16ul
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#define MD_IHIR_iHold 0 // 5 bitts ( (x+1)/32 A )
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#define MD_IHIR_iRun 8 // 5 bits
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#define md_IHIR_iHoldDelay 16 // 4
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// register 0x6C, 7C CHOPCONF
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#define MD_CC1 0X6C
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#define MD_CC2 0X7C
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#define MD_CC1 0x6C
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#define MD_CC2 0x7C
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#define MD_CC_shortProtection 0x40000000
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#define MD_CC_doubbleEdge 0x20000000
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#define MD_CC_16ustapI 0x10000000
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#define MD_CC_mres 24 // 4 bits; 1/(2^x / 2^8) microstappen
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#define MD_CC_vsens 0x00020000
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#define MD_CC_tbl 15 // 3 bits?
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#define MC_CC_FULLSTEP 8ul << MD_CC_mres
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#define MC_CC_2US 7ul << MD_CC_mres
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#define MC_CC_4US 6ul << MD_CC_mres
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#define MC_CC_8US 5ul << MD_CC_mres
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#define MC_CC_16US 4ul << MD_CC_mres
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#define MC_CC_32US 3ul << MD_CC_mres
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#define MC_CC_64US 2ul << MD_CC_mres
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#define MC_CC_128US 1ul << MD_CC_mres
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#define MC_CC_256US 0ul << MD_CC_mres
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#define MD_CC_vsens BIT17
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#define MD_CC_tbl 15 // 2 bits
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#define MD_CC_cmh BIT14
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#define MD_CC_rndtf 0x00002000
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#define MD_CC_disfdcc 0x00001000
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@ -48,21 +60,21 @@ const uchar MD_CS = BIT3;
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#define MD_CC_hstrt 4 // 3 bits
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#define MD_CC_toff 0 // 4 bits
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// bool md_checkError(){
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// unsigned long stat = md_read(MD_GSTAT);
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// if(stat != 0){
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// if(stat == 0x1){ // only a recet has occert
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// // restart the motor driver
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// md_setup();
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// }else{ // one of the motorst stopt due to short or overheated or a undervoltage in chargepump
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// // wait a while for checking again
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// delay(1000);
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// md_checkError();
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// }
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// return true;
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// }
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// return false;
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// }
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enum bool MDStatus(){
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ulong stat = MD_read(MD_GSTAT);
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if(stat != 0){
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if(stat == 0x1){ // only a recet has occert
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// restart the motor driver
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MDInit();
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}else{ // one of the motors stopt due to short or overheated or a undervoltage in chargepump
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// wait a while for checking again
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__delay_cycles(16000000);
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MDStatus();
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}
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return true;
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}
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return false;
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}
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void MD_write(uchar addr, ulong data) {
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char i;
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@ -80,11 +92,11 @@ void MD_write(uchar addr, ulong data) {
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data >>= 8;
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}
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SPISend(SPI_Mode3);
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SPISend();
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}
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unsigned long MD_read(uchar addr) {
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ulong MD_read(uchar addr) {
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char i;
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ulong data;
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@ -95,13 +107,13 @@ unsigned long MD_read(uchar addr) {
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addr &= ~0x80;
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SPI_packet[0] = addr;
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SPISend(SPI_Mode3);
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SPISend();
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// wait for SPI bus to be available
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SPIInitSend(MD_CS, SPI_Mode3, SPI_Clock_4MHz);
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SPI_packet[0] = addr;
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SPISend(SPI_Mode3);
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SPISend();
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// read data
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for(i=2; i<5; i++){
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@ -116,9 +128,13 @@ void MDInit(){
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P1DIR |= MD_CS; // set MD_CS (pin 3) as output
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P1OUT |= MD_CS; // set MD_CS high
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MD_write(MD_GCONF, MD_GCONF_stepdir2Enable | MD_GCONF_stepdir1Enable);
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MD_write(MD_CC1, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI);
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MD_write(MD_CC2, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | (4ul<<MD_CC_mres) | MD_CC_16ustapI);
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MDStatus();
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MD_write(MD_GCONF, MD_GCONF_stepdir2Enable | MD_GCONF_stepdir1Enable | MD_GCONF_motor2Revers);
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MD_write(MD_CC1, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | MC_CC_16US | MD_CC_16ustapI);
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MD_write(MD_CC2, 3ul<<MD_CC_toff | (4ul<<MD_CC_hstrt) | (1ul<<MD_CC_hend) | (2ul<<MD_CC_tbl) | MC_CC_16US | MD_CC_16ustapI);
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MD_write(MD_IHIR1, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay);
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MD_write(MD_IHIR2, 10ul<<MD_IHIR_iHold | 31ul<<MD_IHIR_iRun | 6ul<<md_IHIR_iHoldDelay);
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MDStatus();
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}
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@ -8,6 +8,9 @@
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#ifndef MOTORDRIVER_H_
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#define MOTORDRIVER_H_
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#include "typedefExtention.h"
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void MDInit();
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enum bool MDStatus();
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#endif /* MOTORDRIVER_H_ */
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@ -13,5 +13,39 @@ typedef unsigned char uchar;
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typedef unsigned int uint;
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typedef unsigned long ulong;
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typedef enum bool {false=0, true=1};
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#define BIT00 1ul << 0
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#define BIT01 1ul << 1
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#define BIT02 1ul << 2
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#define BIT03 1ul << 3
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#define BIT04 1ul << 4
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#define BIT05 1ul << 5
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#define BIT06 1ul << 6
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#define BIT07 1ul << 7
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#define BIT08 1ul << 8
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#define BIT09 1ul << 9
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#define BIT10 1ul << 10
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#define BIT11 1ul << 11
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#define BIT12 1ul << 12
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#define BIT13 1ul << 13
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#define BIT14 1ul << 14
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#define BIT15 1ul << 15
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#define BIT16 1ul << 16
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#define BIT17 1ul << 17
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#define BIT18 1ul << 18
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#define BIT19 1ul << 19
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#define BIT20 1ul << 20
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#define BIT21 1ul << 21
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#define BIT22 1ul << 22
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#define BIT23 1ul << 23
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#define BIT24 1ul << 24
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#define BIT25 1ul << 25
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#define BIT26 1ul << 26
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#define BIT27 1ul << 27
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#define BIT28 1ul << 28
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#define BIT29 1ul << 29
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#define BIT30 1ul << 30
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#define BIT31 1ul << 31
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#endif /* TYPEDEFEXTENTION_H_ */
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