104 lines
3.7 KiB
C
104 lines
3.7 KiB
C
/**
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// Example of writing via DMA to the SPI interface and similarly reading it back via a loopback.
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#include <stdio.h>
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#include <stdlib.h>
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#include "pico/stdlib.h"
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#include "hardware/spi.h"
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#include "hardware/dma.h"
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#define PIN_MISO 16
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#define PIN_CS 17
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#define PIN_SCK 18
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#define PIN_MOSI 19
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#define SPI_INST spi0
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#define TEST_SIZE 1024
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int main() {
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// Enable UART so we can print status output
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stdio_init_all();
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printf("SPI DMA example\n");
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// Enable SPI at 1 MHz and connect to GPIOs
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spi_init(SPI_INST, 1000 * 1000);
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gpio_set_function(PIN_MISO, GPIO_FUNC_SPI);
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gpio_init(PIN_CS);
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gpio_set_function(PIN_SCK, GPIO_FUNC_SPI);
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gpio_set_function(PIN_MOSI, GPIO_FUNC_SPI);
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// Grab some unused dma channels
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const uint dma_tx = dma_claim_unused_channel(true);
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const uint dma_rx = dma_claim_unused_channel(true);
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// Force loopback for testing (I don't have an SPI device handy)
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hw_set_bits(&spi_get_hw(SPI_INST)->cr1, SPI_SSPCR1_LBM_BITS);
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static uint8_t txbuf[TEST_SIZE];
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static uint8_t rxbuf[TEST_SIZE];
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for (uint i = 0; i < TEST_SIZE; ++i) {
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txbuf[i] = rand();
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}
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// We set the outbound DMA to transfer from a memory buffer to the SPI transmit FIFO paced by the SPI TX FIFO DREQ
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// The default is for the read address to increment every element (in this case 1 byte - DMA_SIZE_8)
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// and for the write address to remain unchanged.
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printf("Configure TX DMA\n");
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dma_channel_config c = dma_channel_get_default_config(dma_tx);
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channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
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channel_config_set_dreq(&c, spi_get_index(SPI_INST) ? DREQ_SPI1_TX : DREQ_SPI0_TX);
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dma_channel_configure(dma_tx, &c,
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&spi_get_hw(SPI_INST)->dr, // write address
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txbuf, // read address
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TEST_SIZE, // element count (each element is of size transfer_data_size)
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false); // don't start yet
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printf("Configure RX DMA\n");
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// We set the inbound DMA to transfer from the SPI receive FIFO to a memory buffer paced by the SPI RX FIFO DREQ
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// We coinfigure the read address to remain unchanged for each element, but the write
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// address to increment (so data is written throughout the buffer)
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c = dma_channel_get_default_config(dma_rx);
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channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
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channel_config_set_dreq(&c, spi_get_index(SPI_INST) ? DREQ_SPI1_RX : DREQ_SPI0_RX);
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channel_config_set_read_increment(&c, false);
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channel_config_set_write_increment(&c, true);
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dma_channel_configure(dma_rx, &c,
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rxbuf, // write address
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&spi_get_hw(SPI_INST)->dr, // read address
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TEST_SIZE, // element count (each element is of size transfer_data_size)
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false); // don't start yet
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printf("Starting DMAs...\n");
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// start them exactly simultaneously to avoid races (in extreme cases the FIFO could overflow)
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dma_start_channel_mask((1u << dma_tx) | (1u << dma_rx));
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printf("Wait for RX complete...\n");
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dma_channel_wait_for_finish_blocking(dma_rx);
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if (dma_channel_is_busy(dma_tx)) {
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panic("RX completed before TX");
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}
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printf("Done. Checking...");
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for (uint i = 0; i < TEST_SIZE; ++i) {
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if (rxbuf[i] != txbuf[i]) {
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panic("Mismatch at %d/%d: expected %02x, got %02x",
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i, TEST_SIZE, txbuf[i], rxbuf[i]
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);
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}
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}
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printf("All good\n");
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dma_channel_unclaim(dma_tx);
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dma_channel_unclaim(dma_rx);
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return 0;
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}
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