160 lines
6.5 KiB
C
160 lines
6.5 KiB
C
/**
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// PIO logic analyser example
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//
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// This program captures samples from a group of pins, at a fixed rate, once a
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// trigger condition is detected (level condition on one pin). The samples are
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// transferred to a capture buffer using the system DMA.
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//
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// 1 to 32 pins can be captured, at a sample rate no greater than system clock
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// frequency.
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#include <stdio.h>
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#include <stdlib.h>
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#include "pico/stdlib.h"
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#include "hardware/pio.h"
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#include "hardware/dma.h"
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#include "hardware/structs/bus_ctrl.h"
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// Some logic to analyse:
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#include "hardware/structs/pwm.h"
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const uint CAPTURE_PIN_BASE = 16;
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const uint CAPTURE_PIN_COUNT = 2;
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const uint CAPTURE_N_SAMPLES = 96;
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static inline uint bits_packed_per_word(uint pin_count) {
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// If the number of pins to be sampled divides the shift register size, we
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// can use the full SR and FIFO width, and push when the input shift count
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// exactly reaches 32. If not, we have to push earlier, so we use the FIFO
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// a little less efficiently.
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const uint SHIFT_REG_WIDTH = 32;
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return SHIFT_REG_WIDTH - (SHIFT_REG_WIDTH % pin_count);
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}
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void logic_analyser_init(PIO pio, uint sm, uint pin_base, uint pin_count, float div) {
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// Load a program to capture n pins. This is just a single `in pins, n`
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// instruction with a wrap.
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uint16_t capture_prog_instr = pio_encode_in(pio_pins, pin_count);
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struct pio_program capture_prog = {
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.instructions = &capture_prog_instr,
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.length = 1,
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.origin = -1
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};
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uint offset = pio_add_program(pio, &capture_prog);
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// Configure state machine to loop over this `in` instruction forever,
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// with autopush enabled.
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pio_sm_config c = pio_get_default_sm_config();
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sm_config_set_in_pins(&c, pin_base);
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sm_config_set_wrap(&c, offset, offset);
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sm_config_set_clkdiv(&c, div);
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// Note that we may push at a < 32 bit threshold if pin_count does not
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// divide 32. We are using shift-to-right, so the sample data ends up
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// left-justified in the FIFO in this case, with some zeroes at the LSBs.
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sm_config_set_in_shift(&c, true, true, bits_packed_per_word(pin_count));
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
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pio_sm_init(pio, sm, offset, &c);
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}
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void logic_analyser_arm(PIO pio, uint sm, uint dma_chan, uint32_t *capture_buf, size_t capture_size_words,
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uint trigger_pin, bool trigger_level) {
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pio_sm_set_enabled(pio, sm, false);
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// Need to clear _input shift counter_, as well as FIFO, because there may be
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// partial ISR contents left over from a previous run. sm_restart does this.
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pio_sm_clear_fifos(pio, sm);
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pio_sm_restart(pio, sm);
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dma_channel_config c = dma_channel_get_default_config(dma_chan);
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channel_config_set_read_increment(&c, false);
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channel_config_set_write_increment(&c, true);
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channel_config_set_dreq(&c, pio_get_dreq(pio, sm, false));
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dma_channel_configure(dma_chan, &c,
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capture_buf, // Destination pointer
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&pio->rxf[sm], // Source pointer
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capture_size_words, // Number of transfers
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true // Start immediately
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);
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pio_sm_exec(pio, sm, pio_encode_wait_gpio(trigger_level, trigger_pin));
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pio_sm_set_enabled(pio, sm, true);
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}
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void print_capture_buf(const uint32_t *buf, uint pin_base, uint pin_count, uint32_t n_samples) {
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// Display the capture buffer in text form, like this:
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// 00: __--__--__--__--__--__--
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// 01: ____----____----____----
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printf("Capture:\n");
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// Each FIFO record may be only partially filled with bits, depending on
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// whether pin_count is a factor of 32.
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uint record_size_bits = bits_packed_per_word(pin_count);
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for (int pin = 0; pin < pin_count; ++pin) {
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printf("%02d: ", pin + pin_base);
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for (int sample = 0; sample < n_samples; ++sample) {
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uint bit_index = pin + sample * pin_count;
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uint word_index = bit_index / record_size_bits;
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// Data is left-justified in each FIFO entry, hence the (32 - record_size_bits) offset
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uint word_mask = 1u << (bit_index % record_size_bits + 32 - record_size_bits);
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printf(buf[word_index] & word_mask ? "-" : "_");
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}
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printf("\n");
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}
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}
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int main() {
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stdio_init_all();
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printf("PIO logic analyser example\n");
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// We're going to capture into a u32 buffer, for best DMA efficiency. Need
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// to be careful of rounding in case the number of pins being sampled
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// isn't a power of 2.
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uint total_sample_bits = CAPTURE_N_SAMPLES * CAPTURE_PIN_COUNT;
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total_sample_bits += bits_packed_per_word(CAPTURE_PIN_COUNT) - 1;
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uint buf_size_words = total_sample_bits / bits_packed_per_word(CAPTURE_PIN_COUNT);
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uint32_t *capture_buf = malloc(buf_size_words * sizeof(uint32_t));
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hard_assert(capture_buf);
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// Grant high bus priority to the DMA, so it can shove the processors out
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// of the way. This should only be needed if you are pushing things up to
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// >16bits/clk here, i.e. if you need to saturate the bus completely.
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bus_ctrl_hw->priority = BUSCTRL_BUS_PRIORITY_DMA_W_BITS | BUSCTRL_BUS_PRIORITY_DMA_R_BITS;
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PIO pio = pio0;
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uint sm = 0;
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uint dma_chan = 0;
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logic_analyser_init(pio, sm, CAPTURE_PIN_BASE, CAPTURE_PIN_COUNT, 1.f);
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printf("Arming trigger\n");
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logic_analyser_arm(pio, sm, dma_chan, capture_buf, buf_size_words, CAPTURE_PIN_BASE, true);
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printf("Starting PWM example\n");
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// PWM example: -----------------------------------------------------------
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gpio_set_function(CAPTURE_PIN_BASE, GPIO_FUNC_PWM);
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gpio_set_function(CAPTURE_PIN_BASE + 1, GPIO_FUNC_PWM);
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// Topmost value of 3: count from 0 to 3 and then wrap, so period is 4 cycles
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pwm_hw->slice[0].top = 3;
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// Divide frequency by two to slow things down a little
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pwm_hw->slice[0].div = 4 << PWM_CH0_DIV_INT_LSB;
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// Set channel A to be high for 1 cycle each period (duty cycle 1/4) and
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// channel B for 3 cycles (duty cycle 3/4)
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pwm_hw->slice[0].cc =
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(1 << PWM_CH0_CC_A_LSB) |
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(3 << PWM_CH0_CC_B_LSB);
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// Enable this PWM slice
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pwm_hw->slice[0].csr = PWM_CH0_CSR_EN_BITS;
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// ------------------------------------------------------------------------
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// The logic analyser should have started capturing as soon as it saw the
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// first transition. Wait until the last sample comes in from the DMA.
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dma_channel_wait_for_finish_blocking(dma_chan);
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print_capture_buf(capture_buf, CAPTURE_PIN_BASE, CAPTURE_PIN_COUNT, CAPTURE_N_SAMPLES);
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}
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