112 lines
4.5 KiB
C
112 lines
4.5 KiB
C
/**
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// Use two DMA channels to make a programmed sequence of data transfers to the
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// UART (a data gather operation). One channel is responsible for transferring
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// the actual data, the other repeatedly reprograms that channel.
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#include <stdio.h>
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#include "pico/stdlib.h"
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#include "hardware/dma.h"
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#include "hardware/structs/uart.h"
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// These buffers will be DMA'd to the UART, one after the other.
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const char word0[] = "Transferring ";
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const char word1[] = "one ";
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const char word2[] = "word ";
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const char word3[] = "at ";
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const char word4[] = "a ";
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const char word5[] = "time.\n";
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// Note the order of the fields here: it's important that the length is before
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// the read address, because the control channel is going to write to the last
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// two registers in alias 3 on the data channel:
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// +0x0 +0x4 +0x8 +0xC (Trigger)
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// Alias 0: READ_ADDR WRITE_ADDR TRANS_COUNT CTRL
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// Alias 1: CTRL READ_ADDR WRITE_ADDR TRANS_COUNT
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// Alias 2: CTRL TRANS_COUNT READ_ADDR WRITE_ADDR
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// Alias 3: CTRL WRITE_ADDR TRANS_COUNT READ_ADDR
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//
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// This will program the transfer count and read address of the data channel,
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// and trigger it. Once the data channel completes, it will restart the
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// control channel (via CHAIN_TO) to load the next two words into its control
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// registers.
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const struct {uint32_t len; const char *data;} control_blocks[] = {
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{count_of(word0) - 1, word0}, // Skip null terminator
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{count_of(word1) - 1, word1},
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{count_of(word2) - 1, word2},
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{count_of(word3) - 1, word3},
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{count_of(word4) - 1, word4},
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{count_of(word5) - 1, word5},
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{0, NULL} // Null trigger to end chain.
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};
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int main() {
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stdio_init_all();
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puts("DMA control block example:");
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// ctrl_chan loads control blocks into data_chan, which executes them.
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int ctrl_chan = dma_claim_unused_channel(true);
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int data_chan = dma_claim_unused_channel(true);
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// The control channel transfers two words into the data channel's control
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// registers, then halts. The write address wraps on a two-word
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// (eight-byte) boundary, so that the control channel writes the same two
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// registers when it is next triggered.
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dma_channel_config c = dma_channel_get_default_config(ctrl_chan);
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channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
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channel_config_set_read_increment(&c, true);
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channel_config_set_write_increment(&c, true);
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channel_config_set_ring(&c, true, 3); // 1 << 3 byte boundary on write ptr
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dma_channel_configure(
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ctrl_chan,
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&c,
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&dma_hw->ch[data_chan].al3_transfer_count, // Initial write address
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&control_blocks[0], // Initial read address
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2, // Halt after each control block
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false // Don't start yet
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);
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// The data channel is set up to write to the UART FIFO (paced by the
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// UART's TX data request signal) and then chain to the control channel
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// once it completes. The control channel programs a new read address and
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// data length, and retriggers the data channel.
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c = dma_channel_get_default_config(data_chan);
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channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
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channel_config_set_dreq(&c, DREQ_UART0_TX + 2 * PICO_DEFAULT_UART);
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// Trigger ctrl_chan when data_chan completes
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channel_config_set_chain_to(&c, ctrl_chan);
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// Raise the IRQ flag when 0 is written to a trigger register (end of chain):
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channel_config_set_irq_quiet(&c, true);
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dma_channel_configure(
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data_chan,
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&c,
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&(PICO_DEFAULT_UART ? uart1_hw : uart0_hw)->dr,
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NULL, // Initial read address and transfer count are unimportant;
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0, // the control channel will reprogram them each time.
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false // Don't start yet.
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);
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// Everything is ready to go. Tell the control channel to load the first
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// control block. Everything is automatic from here.
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dma_start_channel_mask(1u << ctrl_chan);
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// The data channel will assert its IRQ flag when it gets a null trigger,
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// indicating the end of the control block list. We're just going to wait
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// for the IRQ flag instead of setting up an interrupt handler.
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while (!(dma_hw->intr & 1u << data_chan))
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tight_loop_contents();
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dma_hw->ints0 = 1u << data_chan;
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puts("DMA finished.");
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}
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