90 lines
3.4 KiB
C
90 lines
3.4 KiB
C
/**
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* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdio.h>
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#include <string.h>
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#include "pico/stdlib.h"
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#include "pico/time.h"
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#include "hardware/dma.h"
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#include "hardware/structs/ssi.h"
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// This example DMAs 16kB of data from the start of flash to SRAM, and
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// measures the transfer speed.
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//
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// The SSI (flash interface) inside the XIP block has DREQ logic, so we can
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// DMA directly from its FIFOs. Unlike the XIP stream hardware (see
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// flash_xip_stream.c) this can *not* be done whilst code is running from
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// flash, without careful footwork like we do here. The tradeoff is that it's
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// ~2.5x as fast in QSPI mode, ~2x as fast in SPI mode.
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void __no_inline_not_in_flash_func(flash_bulk_read)(uint32_t *rxbuf, uint32_t flash_offs, size_t len,
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uint dma_chan) {
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// SSI must be disabled to set transfer size. If software is executing
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// from flash right now then it's about to have a bad time
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ssi_hw->ssienr = 0;
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ssi_hw->ctrlr1 = len - 1; // NDF, number of data frames
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ssi_hw->dmacr = SSI_DMACR_TDMAE_BITS | SSI_DMACR_RDMAE_BITS;
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ssi_hw->ssienr = 1;
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// Other than NDF, the SSI configuration used for XIP is suitable for a bulk read too.
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// Configure and start the DMA. Note we are avoiding the dma_*() functions
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// as we can't guarantee they'll be inlined
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dma_hw->ch[dma_chan].read_addr = (uint32_t) &ssi_hw->dr0;
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dma_hw->ch[dma_chan].write_addr = (uint32_t) rxbuf;
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dma_hw->ch[dma_chan].transfer_count = len;
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// Must enable DMA byteswap because non-XIP 32-bit flash transfers are
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// big-endian on SSI (we added a hardware tweak to make XIP sensible)
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dma_hw->ch[dma_chan].ctrl_trig =
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DMA_CH0_CTRL_TRIG_BSWAP_BITS |
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DREQ_XIP_SSIRX << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB |
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dma_chan << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB |
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DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS |
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DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB |
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DMA_CH0_CTRL_TRIG_EN_BITS;
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// Now DMA is waiting, kick off the SSI transfer (mode continuation bits in LSBs)
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ssi_hw->dr0 = (flash_offs << 8u) | 0xa0u;
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// Wait for DMA finish
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while (dma_hw->ch[dma_chan].ctrl_trig & DMA_CH0_CTRL_TRIG_BUSY_BITS);
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// Reconfigure SSI before we jump back into flash!
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ssi_hw->ssienr = 0;
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ssi_hw->ctrlr1 = 0; // Single 32-bit data frame per transfer
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ssi_hw->dmacr = 0;
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ssi_hw->ssienr = 1;
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}
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#define DATA_SIZE_WORDS 4096
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uint32_t rxdata[DATA_SIZE_WORDS];
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uint32_t *expect = (uint32_t *) XIP_NOCACHE_NOALLOC_BASE;
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int main() {
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stdio_init_all();
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memset(rxdata, 0, DATA_SIZE_WORDS * sizeof(uint32_t));
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printf("Starting DMA\n");
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uint32_t start_time = time_us_32();
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flash_bulk_read(rxdata, 0, DATA_SIZE_WORDS, 0);
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uint32_t finish_time = time_us_32();
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printf("DMA finished\n");
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float elapsed_time_s = 1e-6f * (finish_time - start_time);
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printf("Transfer speed: %.3f MB/s\n", (sizeof(uint32_t) * DATA_SIZE_WORDS / 1e6f) / elapsed_time_s);
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bool mismatch = false;
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for (int i = 0; i < DATA_SIZE_WORDS; ++i) {
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if (rxdata[i] != expect[i]) {
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printf("Mismatch at %d: expected %08x, got %08x\n", i, expect[i], rxdata[i]);
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mismatch = true;
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break;
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}
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}
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if (!mismatch)
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printf("Data check ok\n");
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} |