diff --git a/dma/control_blocks/control_blocks.c b/dma/control_blocks/control_blocks.c
index 432d4a7..6e0bd7b 100644
--- a/dma/control_blocks/control_blocks.c
+++ b/dma/control_blocks/control_blocks.c
@@ -84,7 +84,7 @@ int main() {
 
     c = dma_channel_get_default_config(data_chan);
     channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
-    channel_config_set_dreq(&c, DREQ_UART0_TX + 2 * uart_get_index(uart_default));
+    channel_config_set_dreq(&c, uart_get_dreq(uart_default, true));
     // Trigger ctrl_chan when data_chan completes
     channel_config_set_chain_to(&c, ctrl_chan);
     // Raise the IRQ flag when 0 is written to a trigger register (end of chain):
diff --git a/spi/spi_dma/spi_dma.c b/spi/spi_dma/spi_dma.c
index 9a9b8b3..d0018dd 100644
--- a/spi/spi_dma/spi_dma.c
+++ b/spi/spi_dma/spi_dma.c
@@ -56,7 +56,7 @@ int main() {
     printf("Configure TX DMA\n");
     dma_channel_config c = dma_channel_get_default_config(dma_tx);
     channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
-    channel_config_set_dreq(&c, spi_get_index(spi_default) ? DREQ_SPI1_TX : DREQ_SPI0_TX);
+    channel_config_set_dreq(&c, spi_get_dreq(spi_default, true));
     dma_channel_configure(dma_tx, &c,
                           &spi_get_hw(spi_default)->dr, // write address
                           txbuf, // read address
@@ -70,7 +70,7 @@ int main() {
     // address to increment (so data is written throughout the buffer)
     c = dma_channel_get_default_config(dma_rx);
     channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
-    channel_config_set_dreq(&c, spi_get_index(spi_default) ? DREQ_SPI1_RX : DREQ_SPI0_RX);
+    channel_config_set_dreq(&c, spi_get_dreq(spi_default, false));
     channel_config_set_read_increment(&c, false);
     channel_config_set_write_increment(&c, true);
     dma_channel_configure(dma_rx, &c,