Basic port to use the HAL blinky
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@ -8,15 +8,17 @@ version = "0.1.0"
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[dependencies]
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cortex-m = { version = "0.7.1", features = ["inline-asm"] }
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cortex-m-rt = "0.6.10"
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embedded-hal = { version = "0.2.5", features=["unproven"] }
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embedded-time = "0.12.0"
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defmt = "0.1.3"
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defmt-rtt = "0.1.0"
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panic-probe = "0.1.0"
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rp2040-pac = { git = "https://github.com/rp-rs/rp2040-pac", branch="main" }
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rp2040-hal = { git = "https://github.com/rp-rs/rp-hal", branch="main" }
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rp2040-boot2 = { git = "https://github.com/rp-rs/rp2040-boot2-rs", branch="main" }
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#rp2040-pac = { path = "../rp2040-pac" }
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#rp2040-boot2 = { path = "../rp2040-boot2-rs" }
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panic-halt = "0.2.0"
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[patch.crates-io]
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cortex-m = { git = "https://github.com/rust-embedded/cortex-m" }
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119
src/main.rs
119
src/main.rs
@ -1,118 +1,43 @@
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//! Blinks the LED on a Pico board
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//!
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//! This will blink an LED attached to GP25, which is the pin the Pico uses for the on-board LED.
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#![no_std]
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#![no_main]
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#![feature(asm)]
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use core::sync::atomic::{AtomicUsize, Ordering};
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use cortex_m_rt::entry;
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use defmt::*;
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use defmt_rtt as _;
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use pac::{watchdog, xosc};
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use embedded_hal::digital::v2::OutputPin;
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use hal::pac;
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use hal::sio::Sio;
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use panic_probe as _;
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use rp2040_pac as pac;
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mod pll;
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mod resets;
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use rp2040_hal as hal;
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#[link_section = ".boot2"]
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#[used]
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pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER;
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#[defmt::timestamp]
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fn timestamp() -> u64 {
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static COUNT: AtomicUsize = AtomicUsize::new(0);
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// NOTE(no-CAS) `timestamps` runs with interrupts disabled
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let n = COUNT.load(Ordering::Relaxed);
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COUNT.store(n + 1, Ordering::Relaxed);
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n as u64
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}
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fn init(
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resets: pac::RESETS,
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watchdog: pac::WATCHDOG,
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clocks: pac::CLOCKS,
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xosc: pac::XOSC,
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pll_sys: pac::PLL_SYS,
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pll_usb: pac::PLL_USB,
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) {
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// Now reset all the peripherals, except QSPI and XIP (we're using those
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// to execute from external flash!)
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let resets = resets::Resets::new(resets);
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// Reset everything except:
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// - QSPI (we're using it to run this code!)
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// - PLLs (it may be suicide if that's what's clocking us)
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resets.reset(!(resets::IO_QSPI | resets::PADS_QSPI | resets::PLL_SYS | resets::PLL_USB));
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resets.unreset_wait(
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resets::ALL
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& !(resets::ADC
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| resets::RTC
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| resets::SPI0
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| resets::SPI1
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| resets::UART0
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| resets::UART1
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| resets::USBCTRL),
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);
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// xosc 12 mhz
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watchdog
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.tick
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.write(|w| unsafe { w.cycles().bits(XOSC_MHZ as u16).enable().set_bit() });
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clocks.clk_sys_resus_ctrl.write(|w| unsafe { w.bits(0) });
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// Enable XOSC
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// TODO extract to HAL module
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const XOSC_MHZ: u32 = 12;
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xosc.ctrl.write(|w| w.freq_range()._1_15mhz());
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let startup_delay = (((XOSC_MHZ * 1_000_000) / 1000) + 128) / 256;
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xosc.startup
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.write(|w| unsafe { w.delay().bits(startup_delay as u16) });
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xosc.ctrl
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.write(|w| w.freq_range()._1_15mhz().enable().enable());
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while !xosc.status.read().stable().bit_is_set() {}
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// Before we touch PLLs, switch sys and ref cleanly away from their aux sources.
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clocks.clk_sys_ctrl.modify(|_, w| w.src().clk_ref());
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while clocks.clk_sys_selected.read().bits() != 1 {}
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clocks.clk_ref_ctrl.modify(|_, w| w.src().rosc_clksrc_ph());
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while clocks.clk_ref_selected.read().bits() != 1 {}
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resets.reset(resets::PLL_SYS | resets::PLL_USB);
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resets.unreset_wait(resets::PLL_SYS | resets::PLL_USB);
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pll::PLL::new(pll_sys).configure(1, 1500_000_000, 6, 2);
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pll::PLL::new(pll_usb).configure(1, 480_000_000, 5, 2);
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}
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#[entry]
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fn main() -> ! {
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let mut pac = pac::Peripherals::take().unwrap();
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info!("Hello World!");
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let p = pac::Peripherals::take().unwrap();
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init(p.RESETS, p.WATCHDOG, p.CLOCKS, p.XOSC, p.PLL_SYS, p.PLL_USB);
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let led_pin = 25;
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let sio = Sio::new(pac.SIO);
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let pins = hal::gpio::Pins::new(
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pac.IO_BANK0,
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pac.PADS_BANK0,
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sio.gpio_bank0,
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&mut pac.RESETS,
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);
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let mut led_pin = pins.gpio25.into_push_pull_output();
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loop {
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info!("on!");
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p.IO_BANK0.gpio[led_pin].gpio_ctrl.write(|w| {
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w.oeover().enable();
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w.outover().high();
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w
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});
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cortex_m::asm::delay(1_000_000);
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led_pin.set_high().unwrap();
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// TODO: Replace with proper 1s delays once we have clocks working
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cortex_m::asm::delay(500_000);
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info!("off!");
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p.IO_BANK0.gpio[led_pin].gpio_ctrl.write(|w| {
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w.oeover().enable();
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w.outover().low();
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w
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});
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cortex_m::asm::delay(1_000_000);
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led_pin.set_low().unwrap();
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cortex_m::asm::delay(500_000);
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}
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}
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59
src/pll.rs
59
src/pll.rs
@ -1,59 +0,0 @@
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use core::ops::Deref;
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use defmt::{assert, *};
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use rp2040_pac as pac;
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const XOSC_MHZ: u32 = 12;
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pub struct PLL<T: Instance> {
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inner: T,
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}
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impl<T: Instance> PLL<T> {
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pub fn new(inner: T) -> Self {
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Self { inner }
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}
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pub fn configure(&mut self, refdiv: u32, vco_freq: u32, post_div1: u8, post_div2: u8) {
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let p = &self.inner;
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// Power off in case it's already running
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p.pwr.reset();
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p.fbdiv_int.reset();
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let ref_mhz = XOSC_MHZ / refdiv;
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p.cs.write(|w| unsafe { w.bits(ref_mhz as _) });
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let fbdiv = vco_freq / (ref_mhz * 1_000_000);
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assert!(fbdiv >= 16 && fbdiv <= 520);
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assert!((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7));
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assert!(post_div2 <= post_div1);
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assert!(ref_mhz <= (vco_freq / 16));
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p.fbdiv_int.write(|w| unsafe { w.bits(fbdiv) });
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p.pwr.modify(|_, w| w.pd().clear_bit().vcopd().clear_bit());
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while !p.cs.read().lock().bits() {}
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p.prim.write(|w| unsafe {
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w.postdiv1().bits(post_div1);
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w.postdiv2().bits(post_div2);
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w
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});
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p.pwr.modify(|_, w| w.postdivpd().clear_bit());
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}
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}
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mod sealed {
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use rp2040_pac as pac;
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pub trait Instance {}
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impl Instance for pac::PLL_SYS {}
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impl Instance for pac::PLL_USB {}
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}
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pub trait Instance: Deref<Target = pac::pll_sys::RegisterBlock> {}
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impl Instance for pac::PLL_SYS {}
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impl Instance for pac::PLL_USB {}
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@ -1,50 +0,0 @@
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use rp2040_pac as pac;
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pub const ALL: u32 = 0x01ffffff;
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pub const USBCTRL: u32 = 0x01000000;
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pub const UART1: u32 = 0x00800000;
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pub const UART0: u32 = 0x00400000;
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pub const TIMER: u32 = 0x00200000;
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pub const TBMAN: u32 = 0x00100000;
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pub const SYSINFO: u32 = 0x00080000;
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pub const SYSCFG: u32 = 0x00040000;
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pub const SPI1: u32 = 0x00020000;
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pub const SPI0: u32 = 0x00010000;
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pub const RTC: u32 = 0x00008000;
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pub const PWM: u32 = 0x00004000;
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pub const PLL_USB: u32 = 0x00002000;
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pub const PLL_SYS: u32 = 0x00001000;
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pub const PIO1: u32 = 0x00000800;
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pub const PIO0: u32 = 0x00000400;
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pub const PADS_QSPI: u32 = 0x00000200;
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pub const PADS_BANK0: u32 = 0x00000100;
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pub const JTAG: u32 = 0x00000080;
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pub const IO_QSPI: u32 = 0x00000040;
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pub const IO_BANK0: u32 = 0x00000020;
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pub const I2C1: u32 = 0x00000010;
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pub const I2C0: u32 = 0x00000008;
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pub const DMA: u32 = 0x00000004;
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pub const BUSCTRL: u32 = 0x00000002;
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pub const ADC: u32 = 0x00000001;
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pub struct Resets {
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inner: pac::RESETS,
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}
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impl Resets {
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pub fn new(inner: pac::RESETS) -> Self {
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Self { inner }
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}
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pub fn reset(&self, bits: u32) {
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self.inner.reset.write(|w| unsafe { w.bits(bits) })
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}
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pub fn unreset_wait(&self, bits: u32) {
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// TODO use the "atomic clear" register version
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self.inner
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.reset
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.modify(|r, w| unsafe { w.bits(r.bits() & !bits) });
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while ((!self.inner.reset_done.read().bits()) & bits) != 0 {}
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}
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}
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