convert rx to esp32-c3
This commit is contained in:
parent
92d9a448b0
commit
0582792028
@ -5,5 +5,5 @@ dependencies:
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type: idf
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type: idf
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version: 5.2.2
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version: 5.2.2
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manifest_hash: 0646c148cf0e35f84678cd2cb46e9929051a1c6db31905f3a584cca01fd1e49a
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manifest_hash: 0646c148cf0e35f84678cd2cb46e9929051a1c6db31905f3a584cca01fd1e49a
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target: esp32c6
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target: esp32c3
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version: 1.0.0
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version: 1.0.0
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@ -8,21 +8,16 @@ CONFIG_SOC_UART_SUPPORTED=y
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CONFIG_SOC_GDMA_SUPPORTED=y
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CONFIG_SOC_GDMA_SUPPORTED=y
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CONFIG_SOC_AHB_GDMA_SUPPORTED=y
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CONFIG_SOC_AHB_GDMA_SUPPORTED=y
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CONFIG_SOC_GPTIMER_SUPPORTED=y
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CONFIG_SOC_GPTIMER_SUPPORTED=y
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CONFIG_SOC_PCNT_SUPPORTED=y
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CONFIG_SOC_MCPWM_SUPPORTED=y
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CONFIG_SOC_TWAI_SUPPORTED=y
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CONFIG_SOC_TWAI_SUPPORTED=y
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CONFIG_SOC_ETM_SUPPORTED=y
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CONFIG_SOC_PARLIO_SUPPORTED=y
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CONFIG_SOC_BT_SUPPORTED=y
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CONFIG_SOC_BT_SUPPORTED=y
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CONFIG_SOC_IEEE802154_SUPPORTED=y
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CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y
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CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y
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CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y
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CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y
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CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y
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CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y
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CONFIG_SOC_XT_WDT_SUPPORTED=y
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CONFIG_SOC_WIFI_SUPPORTED=y
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CONFIG_SOC_WIFI_SUPPORTED=y
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CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y
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CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y
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CONFIG_SOC_ULP_SUPPORTED=y
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CONFIG_SOC_LP_CORE_SUPPORTED=y
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CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y
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CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y
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CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG=y
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CONFIG_SOC_EFUSE_SUPPORTED=y
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CONFIG_SOC_EFUSE_SUPPORTED=y
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CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
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CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
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CONFIG_SOC_RTC_MEM_SUPPORTED=y
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CONFIG_SOC_RTC_MEM_SUPPORTED=y
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@ -39,19 +34,10 @@ CONFIG_SOC_MPI_SUPPORTED=y
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CONFIG_SOC_SHA_SUPPORTED=y
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CONFIG_SOC_SHA_SUPPORTED=y
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CONFIG_SOC_HMAC_SUPPORTED=y
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CONFIG_SOC_HMAC_SUPPORTED=y
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CONFIG_SOC_DIG_SIGN_SUPPORTED=y
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CONFIG_SOC_DIG_SIGN_SUPPORTED=y
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CONFIG_SOC_ECC_SUPPORTED=y
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CONFIG_SOC_FLASH_ENC_SUPPORTED=y
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CONFIG_SOC_FLASH_ENC_SUPPORTED=y
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CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
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CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
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CONFIG_SOC_SDIO_SLAVE_SUPPORTED=y
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CONFIG_SOC_MEMPROT_SUPPORTED=y
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CONFIG_SOC_BOD_SUPPORTED=y
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CONFIG_SOC_BOD_SUPPORTED=y
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CONFIG_SOC_APM_SUPPORTED=y
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CONFIG_SOC_PMU_SUPPORTED=y
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CONFIG_SOC_PAU_SUPPORTED=y
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CONFIG_SOC_LP_TIMER_SUPPORTED=y
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CONFIG_SOC_LP_AON_SUPPORTED=y
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CONFIG_SOC_LP_PERIPHERALS_SUPPORTED=y
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CONFIG_SOC_LP_I2C_SUPPORTED=y
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CONFIG_SOC_ULP_LP_UART_SUPPORTED=y
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CONFIG_SOC_CLK_TREE_SUPPORTED=y
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CONFIG_SOC_CLK_TREE_SUPPORTED=y
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CONFIG_SOC_ASSIST_DEBUG_SUPPORTED=y
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CONFIG_SOC_ASSIST_DEBUG_SUPPORTED=y
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CONFIG_SOC_WDT_SUPPORTED=y
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CONFIG_SOC_WDT_SUPPORTED=y
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@ -62,68 +48,55 @@ CONFIG_SOC_AES_GDMA=y
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CONFIG_SOC_AES_SUPPORT_AES_128=y
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CONFIG_SOC_AES_SUPPORT_AES_128=y
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CONFIG_SOC_AES_SUPPORT_AES_256=y
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CONFIG_SOC_AES_SUPPORT_AES_256=y
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CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
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CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
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CONFIG_SOC_ADC_ARBITER_SUPPORTED=y
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CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y
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CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y
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CONFIG_SOC_ADC_MONITOR_SUPPORTED=y
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CONFIG_SOC_ADC_MONITOR_SUPPORTED=y
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CONFIG_SOC_ADC_DMA_SUPPORTED=y
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CONFIG_SOC_ADC_DMA_SUPPORTED=y
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CONFIG_SOC_ADC_PERIPH_NUM=1
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CONFIG_SOC_ADC_PERIPH_NUM=2
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CONFIG_SOC_ADC_MAX_CHANNEL_NUM=7
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CONFIG_SOC_ADC_MAX_CHANNEL_NUM=5
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CONFIG_SOC_ADC_ATTEN_NUM=4
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CONFIG_SOC_ADC_ATTEN_NUM=4
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CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1
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CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1
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CONFIG_SOC_ADC_PATT_LEN_MAX=8
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CONFIG_SOC_ADC_PATT_LEN_MAX=8
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CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
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CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12
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CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12
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CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2
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CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
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CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2
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CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4
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CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4
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CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
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CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
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CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2
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CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2
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CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333
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CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333
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CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611
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CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611
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CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12
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CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12
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CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
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CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
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CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y
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CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y
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CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y
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CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y
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CONFIG_SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED=y
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CONFIG_SOC_ADC_TEMPERATURE_SHARE_INTR=y
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CONFIG_SOC_ADC_SHARED_POWER=y
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CONFIG_SOC_ADC_SHARED_POWER=y
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CONFIG_SOC_APB_BACKUP_DMA=y
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CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
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CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
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CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
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CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
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CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y
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CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE=0x4000
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CONFIG_SOC_CPU_CORES_NUM=1
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CONFIG_SOC_CPU_CORES_NUM=1
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CONFIG_SOC_CPU_INTR_NUM=32
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CONFIG_SOC_CPU_INTR_NUM=32
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CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y
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CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y
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CONFIG_SOC_INT_PLIC_SUPPORTED=y
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CONFIG_SOC_CPU_BREAKPOINTS_NUM=8
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CONFIG_SOC_CPU_BREAKPOINTS_NUM=4
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CONFIG_SOC_CPU_WATCHPOINTS_NUM=8
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CONFIG_SOC_CPU_WATCHPOINTS_NUM=4
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CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=0x80000000
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CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE=0x80000000
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CONFIG_SOC_CPU_HAS_PMA=y
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CONFIG_SOC_CPU_IDRAM_SPLIT_USING_PMP=y
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CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=3072
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CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=3072
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CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16
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CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16
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CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100
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CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100
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CONFIG_SOC_AHB_GDMA_VERSION=1
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CONFIG_SOC_AHB_GDMA_VERSION=1
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CONFIG_SOC_GDMA_NUM_GROUPS_MAX=1
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CONFIG_SOC_GDMA_NUM_GROUPS_MAX=1
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CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=3
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CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX=3
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CONFIG_SOC_GDMA_SUPPORT_ETM=y
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CONFIG_SOC_ETM_GROUPS=1
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CONFIG_SOC_ETM_CHANNELS_PER_GROUP=50
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CONFIG_SOC_GPIO_PORT=1
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CONFIG_SOC_GPIO_PORT=1
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CONFIG_SOC_GPIO_PIN_COUNT=31
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CONFIG_SOC_GPIO_PIN_COUNT=22
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CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y
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CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y
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CONFIG_SOC_GPIO_FLEX_GLITCH_FILTER_NUM=8
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CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y
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CONFIG_SOC_GPIO_SUPPORT_ETM=y
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CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y
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CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y
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CONFIG_SOC_GPIO_IN_RANGE_MAX=30
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CONFIG_SOC_GPIO_OUT_RANGE_MAX=30
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CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0
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CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x000000007FFFFF00
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CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y
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CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y
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CONFIG_SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP=y
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CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y
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CONFIG_SOC_GPIO_IN_RANGE_MAX=21
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CONFIG_SOC_GPIO_OUT_RANGE_MAX=21
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CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0
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CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x00000000003FFFC0
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CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX=y
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CONFIG_SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX=y
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CONFIG_SOC_RTCIO_PIN_COUNT=8
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CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y
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CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y
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CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y
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CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8
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CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8
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CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8
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CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8
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CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y
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CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y
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@ -131,7 +104,6 @@ CONFIG_SOC_I2C_NUM=1
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CONFIG_SOC_I2C_FIFO_LEN=32
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CONFIG_SOC_I2C_FIFO_LEN=32
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CONFIG_SOC_I2C_CMD_REG_NUM=8
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CONFIG_SOC_I2C_CMD_REG_NUM=8
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CONFIG_SOC_I2C_SUPPORT_SLAVE=y
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CONFIG_SOC_I2C_SUPPORT_SLAVE=y
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CONFIG_SOC_I2C_SUPPORT_HW_FSM_RST=y
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CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y
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CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y
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CONFIG_SOC_I2C_SUPPORT_XTAL=y
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CONFIG_SOC_I2C_SUPPORT_XTAL=y
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CONFIG_SOC_I2C_SUPPORT_RTC=y
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CONFIG_SOC_I2C_SUPPORT_RTC=y
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@ -139,9 +111,6 @@ CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR=y
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CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST=y
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CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST=y
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CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE=y
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CONFIG_SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE=y
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CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS=y
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CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS=y
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CONFIG_SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH=y
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CONFIG_SOC_LP_I2C_NUM=1
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CONFIG_SOC_LP_I2C_FIFO_LEN=16
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CONFIG_SOC_I2S_NUM=1
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CONFIG_SOC_I2S_NUM=1
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CONFIG_SOC_I2S_HW_VERSION_2=y
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CONFIG_SOC_I2S_HW_VERSION_2=y
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CONFIG_SOC_I2S_SUPPORTS_XTAL=y
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CONFIG_SOC_I2S_SUPPORTS_XTAL=y
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@ -151,25 +120,15 @@ CONFIG_SOC_I2S_SUPPORTS_PDM=y
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CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
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CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
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CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2
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CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2
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CONFIG_SOC_I2S_SUPPORTS_TDM=y
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CONFIG_SOC_I2S_SUPPORTS_TDM=y
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CONFIG_SOC_LEDC_SUPPORT_PLL_DIV_CLOCK=y
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CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
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CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
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CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
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CONFIG_SOC_LEDC_CHANNEL_NUM=6
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CONFIG_SOC_LEDC_CHANNEL_NUM=6
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CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=20
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CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14
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CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y
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CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y
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CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED=y
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CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX=16
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CONFIG_SOC_LEDC_FADE_PARAMS_BIT_WIDTH=10
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CONFIG_SOC_MMU_PAGE_SIZE_CONFIGURABLE=y
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CONFIG_SOC_MMU_PERIPH_NUM=1
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CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1
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CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1
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CONFIG_SOC_MMU_DI_VADDR_SHARED=y
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CONFIG_SOC_MMU_PERIPH_NUM=1
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CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
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CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
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CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
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CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
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CONFIG_SOC_PCNT_GROUPS=1
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CONFIG_SOC_PCNT_UNITS_PER_GROUP=4
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CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2
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CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2
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CONFIG_SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE=y
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CONFIG_SOC_RMT_GROUPS=1
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CONFIG_SOC_RMT_GROUPS=1
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CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=2
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CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=2
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CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=2
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CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=2
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@ -179,30 +138,14 @@ CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y
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CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y
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CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y
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CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y
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CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y
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CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y
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CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y
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CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y
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CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y
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CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y
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CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y
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CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y
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CONFIG_SOC_RMT_SUPPORT_XTAL=y
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CONFIG_SOC_RMT_SUPPORT_XTAL=y
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CONFIG_SOC_RMT_SUPPORT_APB=y
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CONFIG_SOC_RMT_SUPPORT_RC_FAST=y
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CONFIG_SOC_RMT_SUPPORT_RC_FAST=y
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CONFIG_SOC_MCPWM_GROUPS=1
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CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128
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CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3
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CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=108
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CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3
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CONFIG_SOC_RTCIO_PIN_COUNT=0
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CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2
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CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2
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CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2
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CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3
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CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y
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CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3
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CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3
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CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y
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CONFIG_SOC_MCPWM_SUPPORT_ETM=y
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CONFIG_SOC_MCPWM_CAPTURE_CLK_FROM_GROUP=y
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CONFIG_SOC_PARLIO_GROUPS=1
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CONFIG_SOC_PARLIO_TX_UNITS_PER_GROUP=1
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CONFIG_SOC_PARLIO_RX_UNITS_PER_GROUP=1
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CONFIG_SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH=16
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CONFIG_SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH=16
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CONFIG_SOC_PARLIO_TX_RX_SHARE_INTERRUPT=y
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CONFIG_SOC_MPI_MEM_BLOCKS_NUM=4
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CONFIG_SOC_MPI_MEM_BLOCKS_NUM=4
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CONFIG_SOC_MPI_OPERATIONS_NUM=3
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CONFIG_SOC_MPI_OPERATIONS_NUM=3
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CONFIG_SOC_RSA_MAX_BIT_LEN=3072
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CONFIG_SOC_RSA_MAX_BIT_LEN=3072
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@ -215,8 +158,7 @@ CONFIG_SOC_SHA_SUPPORT_SHA224=y
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CONFIG_SOC_SHA_SUPPORT_SHA256=y
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CONFIG_SOC_SHA_SUPPORT_SHA256=y
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CONFIG_SOC_SDM_GROUPS=1
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CONFIG_SOC_SDM_GROUPS=1
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CONFIG_SOC_SDM_CHANNELS_PER_GROUP=4
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CONFIG_SOC_SDM_CHANNELS_PER_GROUP=4
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CONFIG_SOC_SDM_CLK_SUPPORT_PLL_F80M=y
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CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
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CONFIG_SOC_SDM_CLK_SUPPORT_XTAL=y
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CONFIG_SOC_SPI_PERIPH_NUM=2
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CONFIG_SOC_SPI_PERIPH_NUM=2
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CONFIG_SOC_SPI_MAX_CS_NUM=6
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CONFIG_SOC_SPI_MAX_CS_NUM=6
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CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
|
CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
|
||||||
@ -225,9 +167,9 @@ CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y
|
|||||||
CONFIG_SOC_SPI_SUPPORT_CD_SIG=y
|
CONFIG_SOC_SPI_SUPPORT_CD_SIG=y
|
||||||
CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y
|
CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y
|
||||||
CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y
|
CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y
|
||||||
|
CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
|
||||||
CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y
|
CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y
|
||||||
CONFIG_SOC_SPI_SUPPORT_CLK_PLL_F80M=y
|
CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y
|
||||||
CONFIG_SOC_SPI_SUPPORT_CLK_RC_FAST=y
|
|
||||||
CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y
|
CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y
|
||||||
CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16
|
CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16
|
||||||
CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y
|
CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y
|
||||||
@ -236,33 +178,30 @@ CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y
|
|||||||
CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y
|
CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y
|
||||||
CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y
|
CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y
|
||||||
CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y
|
CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y
|
||||||
|
CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
|
||||||
CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y
|
CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y
|
||||||
CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
|
CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
|
||||||
CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
|
CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
|
||||||
|
CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y
|
||||||
CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
|
CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
|
||||||
CONFIG_SOC_SYSTIMER_COUNTER_NUM=2
|
CONFIG_SOC_SYSTIMER_COUNTER_NUM=2
|
||||||
CONFIG_SOC_SYSTIMER_ALARM_NUM=3
|
CONFIG_SOC_SYSTIMER_ALARM_NUM=3
|
||||||
CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32
|
CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32
|
||||||
CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20
|
CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20
|
||||||
CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y
|
CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y
|
||||||
CONFIG_SOC_SYSTIMER_SUPPORT_RC_FAST=y
|
|
||||||
CONFIG_SOC_SYSTIMER_INT_LEVEL=y
|
CONFIG_SOC_SYSTIMER_INT_LEVEL=y
|
||||||
CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y
|
CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y
|
||||||
CONFIG_SOC_SYSTIMER_SUPPORT_ETM=y
|
|
||||||
CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO=32
|
|
||||||
CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI=16
|
|
||||||
CONFIG_SOC_TIMER_GROUPS=2
|
CONFIG_SOC_TIMER_GROUPS=2
|
||||||
CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1
|
CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1
|
||||||
CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54
|
CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54
|
||||||
CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y
|
CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y
|
||||||
CONFIG_SOC_TIMER_GROUP_SUPPORT_RC_FAST=y
|
CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
|
||||||
CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=2
|
CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=2
|
||||||
CONFIG_SOC_TIMER_SUPPORT_ETM=y
|
|
||||||
CONFIG_SOC_MWDT_SUPPORT_XTAL=y
|
CONFIG_SOC_MWDT_SUPPORT_XTAL=y
|
||||||
CONFIG_SOC_TWAI_CONTROLLER_NUM=2
|
CONFIG_SOC_TWAI_CONTROLLER_NUM=1
|
||||||
CONFIG_SOC_TWAI_CLK_SUPPORT_XTAL=y
|
CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
|
||||||
CONFIG_SOC_TWAI_BRP_MIN=2
|
CONFIG_SOC_TWAI_BRP_MIN=2
|
||||||
CONFIG_SOC_TWAI_BRP_MAX=32768
|
CONFIG_SOC_TWAI_BRP_MAX=16384
|
||||||
CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y
|
CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y
|
||||||
CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y
|
CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y
|
||||||
CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y
|
CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y
|
||||||
@ -272,87 +211,65 @@ CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y
|
|||||||
CONFIG_SOC_EFUSE_DIS_ICACHE=y
|
CONFIG_SOC_EFUSE_DIS_ICACHE=y
|
||||||
CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y
|
CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y
|
||||||
CONFIG_SOC_SECURE_BOOT_V2_RSA=y
|
CONFIG_SOC_SECURE_BOOT_V2_RSA=y
|
||||||
CONFIG_SOC_SECURE_BOOT_V2_ECC=y
|
|
||||||
CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3
|
CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3
|
||||||
CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y
|
CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y
|
||||||
CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y
|
CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y
|
||||||
CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32
|
CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32
|
||||||
CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y
|
CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y
|
||||||
CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y
|
CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y
|
||||||
CONFIG_SOC_CRYPTO_DPA_PROTECTION_SUPPORTED=y
|
CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
|
||||||
CONFIG_SOC_UART_NUM=3
|
CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=512
|
||||||
|
CONFIG_SOC_UART_NUM=2
|
||||||
CONFIG_SOC_UART_HP_NUM=2
|
CONFIG_SOC_UART_HP_NUM=2
|
||||||
CONFIG_SOC_UART_LP_NUM=1
|
|
||||||
CONFIG_SOC_UART_FIFO_LEN=128
|
CONFIG_SOC_UART_FIFO_LEN=128
|
||||||
CONFIG_SOC_LP_UART_FIFO_LEN=16
|
|
||||||
CONFIG_SOC_UART_BITRATE_MAX=5000000
|
CONFIG_SOC_UART_BITRATE_MAX=5000000
|
||||||
CONFIG_SOC_UART_SUPPORT_PLL_F80M_CLK=y
|
CONFIG_SOC_UART_SUPPORT_APB_CLK=y
|
||||||
CONFIG_SOC_UART_SUPPORT_RTC_CLK=y
|
CONFIG_SOC_UART_SUPPORT_RTC_CLK=y
|
||||||
CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y
|
CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y
|
||||||
CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
|
CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
|
||||||
CONFIG_SOC_UART_HAS_LP_UART=y
|
|
||||||
CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y
|
CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y
|
||||||
CONFIG_SOC_COEX_HW_PTI=y
|
CONFIG_SOC_COEX_HW_PTI=y
|
||||||
CONFIG_SOC_EXTERNAL_COEX_ADVANCE=y
|
|
||||||
CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
|
CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
|
||||||
|
CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192
|
||||||
CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12
|
CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12
|
||||||
CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y
|
CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y
|
||||||
CONFIG_SOC_PM_SUPPORT_BEACON_WAKEUP=y
|
|
||||||
CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y
|
CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y
|
||||||
CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y
|
|
||||||
CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN=y
|
|
||||||
CONFIG_SOC_PM_SUPPORT_CPU_PD=y
|
CONFIG_SOC_PM_SUPPORT_CPU_PD=y
|
||||||
CONFIG_SOC_PM_SUPPORT_MODEM_PD=y
|
CONFIG_SOC_PM_SUPPORT_WIFI_PD=y
|
||||||
CONFIG_SOC_PM_SUPPORT_XTAL32K_PD=y
|
CONFIG_SOC_PM_SUPPORT_BT_PD=y
|
||||||
CONFIG_SOC_PM_SUPPORT_RC32K_PD=y
|
|
||||||
CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
|
CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
|
||||||
CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
|
CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
|
||||||
CONFIG_SOC_PM_SUPPORT_TOP_PD=y
|
|
||||||
CONFIG_SOC_PM_SUPPORT_HP_AON_PD=y
|
|
||||||
CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y
|
CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y
|
||||||
CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y
|
CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y
|
||||||
CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE=y
|
CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y
|
||||||
CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y
|
CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
|
||||||
CONFIG_SOC_PM_CPU_RETENTION_BY_SW=y
|
CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
|
||||||
CONFIG_SOC_PM_MODEM_RETENTION_BY_REGDMA=y
|
|
||||||
CONFIG_SOC_PM_RETENTION_HAS_CLOCK_BUG=y
|
|
||||||
CONFIG_SOC_PM_PAU_LINK_NUM=4
|
|
||||||
CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
|
CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
|
||||||
CONFIG_SOC_MODEM_CLOCK_IS_INDEPENDENT=y
|
|
||||||
CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
|
CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
|
||||||
CONFIG_SOC_CLK_OSC_SLOW_SUPPORTED=y
|
|
||||||
CONFIG_SOC_CLK_RC32K_SUPPORTED=y
|
|
||||||
CONFIG_SOC_RCC_IS_INDEPENDENT=y
|
|
||||||
CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
|
CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
|
||||||
CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y
|
CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y
|
||||||
CONFIG_SOC_TEMPERATURE_SENSOR_INTR_SUPPORT=y
|
|
||||||
CONFIG_SOC_WIFI_HW_TSF=y
|
CONFIG_SOC_WIFI_HW_TSF=y
|
||||||
CONFIG_SOC_WIFI_FTM_SUPPORT=y
|
CONFIG_SOC_WIFI_FTM_SUPPORT=y
|
||||||
CONFIG_SOC_WIFI_GCMP_SUPPORT=y
|
CONFIG_SOC_WIFI_GCMP_SUPPORT=y
|
||||||
CONFIG_SOC_WIFI_WAPI_SUPPORT=y
|
CONFIG_SOC_WIFI_WAPI_SUPPORT=y
|
||||||
CONFIG_SOC_WIFI_CSI_SUPPORT=y
|
CONFIG_SOC_WIFI_CSI_SUPPORT=y
|
||||||
CONFIG_SOC_WIFI_MESH_SUPPORT=y
|
CONFIG_SOC_WIFI_MESH_SUPPORT=y
|
||||||
CONFIG_SOC_WIFI_HE_SUPPORT=y
|
CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
|
||||||
|
CONFIG_SOC_WIFI_PHY_NEEDS_USB_WORKAROUND=y
|
||||||
CONFIG_SOC_BLE_SUPPORTED=y
|
CONFIG_SOC_BLE_SUPPORTED=y
|
||||||
CONFIG_SOC_BLE_MESH_SUPPORTED=y
|
CONFIG_SOC_BLE_MESH_SUPPORTED=y
|
||||||
CONFIG_SOC_ESP_NIMBLE_CONTROLLER=y
|
|
||||||
CONFIG_SOC_BLE_50_SUPPORTED=y
|
CONFIG_SOC_BLE_50_SUPPORTED=y
|
||||||
CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y
|
CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y
|
||||||
CONFIG_SOC_BLE_POWER_CONTROL_SUPPORTED=y
|
|
||||||
CONFIG_SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED=y
|
|
||||||
CONFIG_SOC_BLUFI_SUPPORTED=y
|
CONFIG_SOC_BLUFI_SUPPORTED=y
|
||||||
CONFIG_SOC_BLE_MULTI_CONN_OPTIMIZATION=y
|
|
||||||
CONFIG_SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND=y
|
|
||||||
CONFIG_SOC_PHY_COMBO_MODULE=y
|
CONFIG_SOC_PHY_COMBO_MODULE=y
|
||||||
CONFIG_SOC_CAPS_NO_RESET_BY_ANA_BOD=y
|
|
||||||
CONFIG_IDF_CMAKE=y
|
CONFIG_IDF_CMAKE=y
|
||||||
CONFIG_IDF_TOOLCHAIN="gcc"
|
CONFIG_IDF_TOOLCHAIN="gcc"
|
||||||
CONFIG_IDF_TARGET_ARCH_RISCV=y
|
CONFIG_IDF_TARGET_ARCH_RISCV=y
|
||||||
CONFIG_IDF_TARGET_ARCH="riscv"
|
CONFIG_IDF_TARGET_ARCH="riscv"
|
||||||
CONFIG_IDF_TARGET="esp32c6"
|
CONFIG_IDF_TARGET="esp32c3"
|
||||||
CONFIG_IDF_INIT_VERSION="5.2.2"
|
CONFIG_IDF_INIT_VERSION="5.2.2"
|
||||||
CONFIG_IDF_TARGET_ESP32C6=y
|
CONFIG_IDF_TARGET_ESP32C3=y
|
||||||
CONFIG_IDF_FIRMWARE_CHIP_ID=0x000D
|
CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005
|
||||||
|
|
||||||
#
|
#
|
||||||
# Build type
|
# Build type
|
||||||
@ -381,6 +298,7 @@ CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0
|
|||||||
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
|
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
|
||||||
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
|
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
|
||||||
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set
|
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set
|
||||||
|
# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set
|
||||||
# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
|
# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
|
||||||
# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
|
# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
|
||||||
# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set
|
# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set
|
||||||
@ -414,7 +332,6 @@ CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0
|
|||||||
# Security features
|
# Security features
|
||||||
#
|
#
|
||||||
CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y
|
CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y
|
||||||
CONFIG_SECURE_BOOT_V2_ECC_SUPPORTED=y
|
|
||||||
CONFIG_SECURE_BOOT_V2_PREFERRED=y
|
CONFIG_SECURE_BOOT_V2_PREFERRED=y
|
||||||
# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
|
# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
|
||||||
# CONFIG_SECURE_BOOT is not set
|
# CONFIG_SECURE_BOOT is not set
|
||||||
@ -434,21 +351,19 @@ CONFIG_APP_RETRIEVE_LEN_ELF_SHA=9
|
|||||||
|
|
||||||
CONFIG_ESP_ROM_HAS_CRC_LE=y
|
CONFIG_ESP_ROM_HAS_CRC_LE=y
|
||||||
CONFIG_ESP_ROM_HAS_CRC_BE=y
|
CONFIG_ESP_ROM_HAS_CRC_BE=y
|
||||||
|
CONFIG_ESP_ROM_HAS_MZ_CRC32=y
|
||||||
CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
|
CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
|
||||||
CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y
|
CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y
|
||||||
CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=3
|
CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=3
|
||||||
CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y
|
CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y
|
||||||
|
CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y
|
||||||
|
CONFIG_ESP_ROM_HAS_ENCRYPTED_WRITES_USING_LEGACY_DRV=y
|
||||||
CONFIG_ESP_ROM_GET_CLK_FREQ=y
|
CONFIG_ESP_ROM_GET_CLK_FREQ=y
|
||||||
CONFIG_ESP_ROM_HAS_RVFPLIB=y
|
CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
|
||||||
CONFIG_ESP_ROM_HAS_HAL_WDT=y
|
|
||||||
CONFIG_ESP_ROM_HAS_HAL_SYSTIMER=y
|
|
||||||
CONFIG_ESP_ROM_HAS_HEAP_TLSF=y
|
|
||||||
CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y
|
CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y
|
||||||
CONFIG_ESP_ROM_HAS_SPI_FLASH=y
|
CONFIG_ESP_ROM_HAS_SPI_FLASH=y
|
||||||
CONFIG_ESP_ROM_HAS_REGI2C_BUG=y
|
CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y
|
||||||
CONFIG_ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT=y
|
CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
|
||||||
CONFIG_ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE=y
|
|
||||||
CONFIG_ESP_ROM_WDT_INIT_PATCH=y
|
|
||||||
CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y
|
CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y
|
||||||
CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y
|
CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y
|
||||||
CONFIG_ESP_ROM_HAS_SW_FLOAT=y
|
CONFIG_ESP_ROM_HAS_SW_FLOAT=y
|
||||||
@ -474,6 +389,7 @@ CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
|
|||||||
CONFIG_ESPTOOLPY_FLASHMODE="dio"
|
CONFIG_ESPTOOLPY_FLASHMODE="dio"
|
||||||
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
|
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
|
||||||
# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set
|
# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set
|
||||||
|
# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set
|
||||||
# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
|
# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
|
||||||
CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y
|
CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y
|
||||||
CONFIG_ESPTOOLPY_FLASHFREQ="80m"
|
CONFIG_ESPTOOLPY_FLASHFREQ="80m"
|
||||||
@ -519,8 +435,7 @@ CONFIG_COMPILER_OPTIMIZATION_DEBUG=y
|
|||||||
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
|
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
|
||||||
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
|
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
|
||||||
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
|
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
|
||||||
# CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB is not set
|
CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
|
||||||
CONFIG_COMPILER_FLOAT_LIB_FROM_RVFPLIB=y
|
|
||||||
CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
|
CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
|
||||||
# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
|
# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
|
||||||
CONFIG_COMPILER_HIDE_PATHS_MACROS=y
|
CONFIG_COMPILER_HIDE_PATHS_MACROS=y
|
||||||
@ -549,7 +464,7 @@ CONFIG_COMPILER_RT_LIB_NAME="gcc"
|
|||||||
# CONFIG_APPTRACE_DEST_JTAG is not set
|
# CONFIG_APPTRACE_DEST_JTAG is not set
|
||||||
CONFIG_APPTRACE_DEST_NONE=y
|
CONFIG_APPTRACE_DEST_NONE=y
|
||||||
# CONFIG_APPTRACE_DEST_UART1 is not set
|
# CONFIG_APPTRACE_DEST_UART1 is not set
|
||||||
# CONFIG_APPTRACE_DEST_UART2 is not set
|
# CONFIG_APPTRACE_DEST_USB_CDC is not set
|
||||||
CONFIG_APPTRACE_DEST_UART_NONE=y
|
CONFIG_APPTRACE_DEST_UART_NONE=y
|
||||||
CONFIG_APPTRACE_UART_TASK_PRIO=1
|
CONFIG_APPTRACE_UART_TASK_PRIO=1
|
||||||
CONFIG_APPTRACE_LOCK_ENABLE=y
|
CONFIG_APPTRACE_LOCK_ENABLE=y
|
||||||
@ -591,6 +506,7 @@ CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
|
|||||||
# TWAI Configuration
|
# TWAI Configuration
|
||||||
#
|
#
|
||||||
# CONFIG_TWAI_ISR_IN_IRAM is not set
|
# CONFIG_TWAI_ISR_IN_IRAM is not set
|
||||||
|
CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
|
||||||
# end of TWAI Configuration
|
# end of TWAI Configuration
|
||||||
|
|
||||||
#
|
#
|
||||||
@ -598,7 +514,6 @@ CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
|
|||||||
#
|
#
|
||||||
# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set
|
# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set
|
||||||
# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
|
# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
|
||||||
# CONFIG_TEMP_SENSOR_ISR_IRAM_SAFE is not set
|
|
||||||
# end of Temperature sensor Configuration
|
# end of Temperature sensor Configuration
|
||||||
|
|
||||||
#
|
#
|
||||||
@ -631,15 +546,6 @@ CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y
|
|||||||
# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
|
# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
|
||||||
# end of GPTimer Configuration
|
# end of GPTimer Configuration
|
||||||
|
|
||||||
#
|
|
||||||
# PCNT Configuration
|
|
||||||
#
|
|
||||||
# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set
|
|
||||||
# CONFIG_PCNT_ISR_IRAM_SAFE is not set
|
|
||||||
# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set
|
|
||||||
# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set
|
|
||||||
# end of PCNT Configuration
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# RMT Configuration
|
# RMT Configuration
|
||||||
#
|
#
|
||||||
@ -649,15 +555,6 @@ CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y
|
|||||||
# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
|
# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
|
||||||
# end of RMT Configuration
|
# end of RMT Configuration
|
||||||
|
|
||||||
#
|
|
||||||
# MCPWM Configuration
|
|
||||||
#
|
|
||||||
# CONFIG_MCPWM_ISR_IRAM_SAFE is not set
|
|
||||||
# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set
|
|
||||||
# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set
|
|
||||||
# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set
|
|
||||||
# end of MCPWM Configuration
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# I2S Configuration
|
# I2S Configuration
|
||||||
#
|
#
|
||||||
@ -671,13 +568,6 @@ CONFIG_GPTIMER_ISR_HANDLER_IN_IRAM=y
|
|||||||
#
|
#
|
||||||
# end of USB Serial/JTAG Configuration
|
# end of USB Serial/JTAG Configuration
|
||||||
|
|
||||||
#
|
|
||||||
# Parallel IO Configuration
|
|
||||||
#
|
|
||||||
# CONFIG_PARLIO_ENABLE_DEBUG_LOG is not set
|
|
||||||
# CONFIG_PARLIO_ISR_IRAM_SAFE is not set
|
|
||||||
# end of Parallel IO Configuration
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# LEDC Configuration
|
# LEDC Configuration
|
||||||
#
|
#
|
||||||
@ -716,12 +606,13 @@ CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
|
|||||||
#
|
#
|
||||||
# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
|
# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
|
||||||
# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
|
# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
|
||||||
|
# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set
|
||||||
|
# CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 is not set
|
||||||
# end of ADC and ADC Calibration
|
# end of ADC and ADC Calibration
|
||||||
|
|
||||||
#
|
#
|
||||||
# Wireless Coexistence
|
# Wireless Coexistence
|
||||||
#
|
#
|
||||||
CONFIG_ESP_COEX_SW_COEXIST_ENABLE=y
|
|
||||||
# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set
|
# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set
|
||||||
# end of Wireless Coexistence
|
# end of Wireless Coexistence
|
||||||
|
|
||||||
@ -800,16 +691,20 @@ CONFIG_HTTPD_PURGE_BUF_LEN=32
|
|||||||
#
|
#
|
||||||
# Chip revision
|
# Chip revision
|
||||||
#
|
#
|
||||||
CONFIG_ESP32C6_REV_MIN_0=y
|
# CONFIG_ESP32C3_REV_MIN_0 is not set
|
||||||
# CONFIG_ESP32C6_REV_MIN_1 is not set
|
# CONFIG_ESP32C3_REV_MIN_1 is not set
|
||||||
CONFIG_ESP32C6_REV_MIN_FULL=0
|
# CONFIG_ESP32C3_REV_MIN_2 is not set
|
||||||
CONFIG_ESP_REV_MIN_FULL=0
|
CONFIG_ESP32C3_REV_MIN_3=y
|
||||||
|
# CONFIG_ESP32C3_REV_MIN_4 is not set
|
||||||
|
# CONFIG_ESP32C3_REV_MIN_101 is not set
|
||||||
|
CONFIG_ESP32C3_REV_MIN_FULL=3
|
||||||
|
CONFIG_ESP_REV_MIN_FULL=3
|
||||||
|
|
||||||
#
|
#
|
||||||
# Maximum Supported ESP32-C6 Revision (Rev v0.99)
|
# Maximum Supported ESP32-C3 Revision (Rev v1.99)
|
||||||
#
|
#
|
||||||
CONFIG_ESP32C6_REV_MAX_FULL=99
|
CONFIG_ESP32C3_REV_MAX_FULL=199
|
||||||
CONFIG_ESP_REV_MAX_FULL=99
|
CONFIG_ESP_REV_MAX_FULL=199
|
||||||
# end of Chip revision
|
# end of Chip revision
|
||||||
|
|
||||||
#
|
#
|
||||||
@ -819,11 +714,10 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
|
|||||||
CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
|
CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
|
||||||
CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
|
CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
|
||||||
CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
|
CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
|
||||||
CONFIG_ESP_MAC_ADDR_UNIVERSE_IEEE802154=y
|
|
||||||
CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
|
CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
|
||||||
# CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES_TWO is not set
|
# CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO is not set
|
||||||
CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR=y
|
CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR=y
|
||||||
CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES=4
|
CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES=4
|
||||||
# CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set
|
# CONFIG_ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC is not set
|
||||||
# end of MAC Config
|
# end of MAC Config
|
||||||
|
|
||||||
@ -840,13 +734,15 @@ CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY=0
|
|||||||
CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y
|
CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS=y
|
||||||
# end of Sleep Config
|
# end of Sleep Config
|
||||||
|
|
||||||
|
CONFIG_ESP_SLEEP_SYSTIMER_STALL_WORKAROUND=y
|
||||||
|
|
||||||
#
|
#
|
||||||
# RTC Clock Config
|
# RTC Clock Config
|
||||||
#
|
#
|
||||||
CONFIG_RTC_CLK_SRC_INT_RC=y
|
CONFIG_RTC_CLK_SRC_INT_RC=y
|
||||||
# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
|
# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
|
||||||
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
|
# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
|
||||||
# CONFIG_RTC_CLK_SRC_INT_RC32K is not set
|
# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
|
||||||
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
CONFIG_RTC_CLK_CAL_CYCLES=1024
|
||||||
# end of RTC Clock Config
|
# end of RTC Clock Config
|
||||||
|
|
||||||
@ -856,12 +752,6 @@ CONFIG_RTC_CLK_CAL_CYCLES=1024
|
|||||||
CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
|
CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
|
||||||
# end of Peripheral Control
|
# end of Peripheral Control
|
||||||
|
|
||||||
#
|
|
||||||
# ETM Configuration
|
|
||||||
#
|
|
||||||
# CONFIG_ETM_ENABLE_DEBUG_LOG is not set
|
|
||||||
# end of ETM Configuration
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# GDMA Configuration
|
# GDMA Configuration
|
||||||
#
|
#
|
||||||
@ -876,16 +766,6 @@ CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
|
|||||||
CONFIG_XTAL_FREQ_40=y
|
CONFIG_XTAL_FREQ_40=y
|
||||||
CONFIG_XTAL_FREQ=40
|
CONFIG_XTAL_FREQ=40
|
||||||
# end of Main XTAL Config
|
# end of Main XTAL Config
|
||||||
|
|
||||||
#
|
|
||||||
# Crypto DPA Protection
|
|
||||||
#
|
|
||||||
CONFIG_ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP=y
|
|
||||||
CONFIG_ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW=y
|
|
||||||
# CONFIG_ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM is not set
|
|
||||||
# CONFIG_ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH is not set
|
|
||||||
CONFIG_ESP_CRYPTO_DPA_PROTECTION_LEVEL=1
|
|
||||||
# end of Crypto DPA Protection
|
|
||||||
# end of Hardware Settings
|
# end of Hardware Settings
|
||||||
|
|
||||||
#
|
#
|
||||||
@ -929,6 +809,8 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
|
|||||||
CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
|
CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
|
||||||
CONFIG_ESP_PHY_MAX_TX_POWER=20
|
CONFIG_ESP_PHY_MAX_TX_POWER=20
|
||||||
# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
|
# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
|
||||||
|
CONFIG_ESP_PHY_ENABLE_USB=y
|
||||||
|
# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set
|
||||||
CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
|
CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
|
||||||
# CONFIG_ESP_PHY_RF_CAL_NONE is not set
|
# CONFIG_ESP_PHY_RF_CAL_NONE is not set
|
||||||
# CONFIG_ESP_PHY_RF_CAL_FULL is not set
|
# CONFIG_ESP_PHY_RF_CAL_FULL is not set
|
||||||
@ -941,7 +823,6 @@ CONFIG_ESP_PHY_CALIBRATION_MODE=0
|
|||||||
#
|
#
|
||||||
# CONFIG_PM_ENABLE is not set
|
# CONFIG_PM_ENABLE is not set
|
||||||
CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
|
CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
|
||||||
# CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is not set
|
|
||||||
# end of Power Management
|
# end of Power Management
|
||||||
|
|
||||||
#
|
#
|
||||||
@ -958,7 +839,6 @@ CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
|
|||||||
# ESP System Settings
|
# ESP System Settings
|
||||||
#
|
#
|
||||||
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
|
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
|
||||||
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_120 is not set
|
|
||||||
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
|
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
|
||||||
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
|
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
|
||||||
# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
|
# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
|
||||||
@ -974,7 +854,8 @@ CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
|
|||||||
#
|
#
|
||||||
# Memory protection
|
# Memory protection
|
||||||
#
|
#
|
||||||
CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT=y
|
CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y
|
||||||
|
CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y
|
||||||
# end of Memory protection
|
# end of Memory protection
|
||||||
|
|
||||||
CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
|
CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
|
||||||
@ -1021,7 +902,6 @@ CONFIG_ESP_BROWNOUT_DET_LVL=7
|
|||||||
|
|
||||||
CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
|
CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
|
||||||
CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y
|
CONFIG_ESP_SYSTEM_HW_STACK_GUARD=y
|
||||||
CONFIG_ESP_SYSTEM_BBPLL_RECALIB=y
|
|
||||||
# end of ESP System Settings
|
# end of ESP System Settings
|
||||||
|
|
||||||
#
|
#
|
||||||
@ -1070,7 +950,7 @@ CONFIG_ESP_WIFI_NVS_ENABLED=y
|
|||||||
CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
|
CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
|
||||||
CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
|
CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
|
||||||
CONFIG_ESP_WIFI_IRAM_OPT=y
|
CONFIG_ESP_WIFI_IRAM_OPT=y
|
||||||
CONFIG_ESP_WIFI_EXTRA_IRAM_OPT=y
|
# CONFIG_ESP_WIFI_EXTRA_IRAM_OPT is not set
|
||||||
CONFIG_ESP_WIFI_RX_IRAM_OPT=y
|
CONFIG_ESP_WIFI_RX_IRAM_OPT=y
|
||||||
CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
|
CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
|
||||||
CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
|
CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
|
||||||
@ -1084,7 +964,6 @@ CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE=y
|
|||||||
CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
|
CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
|
||||||
# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
|
# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
|
||||||
CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
|
CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
|
||||||
CONFIG_ESP_WIFI_ENABLE_WIFI_TX_STATS=y
|
|
||||||
CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
|
CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
|
||||||
CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
|
CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
|
||||||
# CONFIG_ESP_WIFI_WAPI_PSK is not set
|
# CONFIG_ESP_WIFI_WAPI_PSK is not set
|
||||||
@ -1094,8 +973,6 @@ CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
|
|||||||
# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
|
# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
|
||||||
# CONFIG_ESP_WIFI_11R_SUPPORT is not set
|
# CONFIG_ESP_WIFI_11R_SUPPORT is not set
|
||||||
# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
|
# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
|
||||||
CONFIG_ESP_WIFI_ENABLE_WIFI_RX_STATS=y
|
|
||||||
CONFIG_ESP_WIFI_ENABLE_WIFI_RX_MU_STATS=y
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# WPS Configuration Options
|
# WPS Configuration Options
|
||||||
@ -1224,8 +1101,6 @@ CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
|
|||||||
# CONFIG_HAL_ASSERTION_SILENT is not set
|
# CONFIG_HAL_ASSERTION_SILENT is not set
|
||||||
# CONFIG_HAL_ASSERTION_ENABLE is not set
|
# CONFIG_HAL_ASSERTION_ENABLE is not set
|
||||||
CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
|
CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
|
||||||
CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=y
|
|
||||||
CONFIG_HAL_WDT_USE_ROM_IMPL=y
|
|
||||||
CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
|
CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
|
||||||
CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
|
CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
|
||||||
# end of Hardware Abstraction Layer (HAL) and Low Level (LL)
|
# end of Hardware Abstraction Layer (HAL) and Low Level (LL)
|
||||||
@ -1242,26 +1117,9 @@ CONFIG_HEAP_TRACING_OFF=y
|
|||||||
# CONFIG_HEAP_USE_HOOKS is not set
|
# CONFIG_HEAP_USE_HOOKS is not set
|
||||||
# CONFIG_HEAP_TASK_TRACKING is not set
|
# CONFIG_HEAP_TASK_TRACKING is not set
|
||||||
# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
|
# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
|
||||||
CONFIG_HEAP_TLSF_USE_ROM_IMPL=y
|
# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
|
||||||
# end of Heap memory debugging
|
# end of Heap memory debugging
|
||||||
|
|
||||||
#
|
|
||||||
# IEEE 802.15.4
|
|
||||||
#
|
|
||||||
CONFIG_IEEE802154_ENABLED=y
|
|
||||||
CONFIG_IEEE802154_RX_BUFFER_SIZE=20
|
|
||||||
# CONFIG_IEEE802154_CCA_CARRIER is not set
|
|
||||||
CONFIG_IEEE802154_CCA_ED=y
|
|
||||||
# CONFIG_IEEE802154_CCA_CARRIER_OR_ED is not set
|
|
||||||
# CONFIG_IEEE802154_CCA_CARRIER_AND_ED is not set
|
|
||||||
CONFIG_IEEE802154_CCA_MODE=1
|
|
||||||
CONFIG_IEEE802154_CCA_THRESHOLD=-60
|
|
||||||
CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
|
|
||||||
# CONFIG_IEEE802154_MULTI_PAN_ENABLE is not set
|
|
||||||
# CONFIG_IEEE802154_TIMING_OPTIMIZATION is not set
|
|
||||||
# CONFIG_IEEE802154_DEBUG is not set
|
|
||||||
# end of IEEE 802.15.4
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# Log output
|
# Log output
|
||||||
#
|
#
|
||||||
@ -1497,8 +1355,6 @@ CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI=y
|
|||||||
CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
|
CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
|
||||||
CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL=0
|
CONFIG_MBEDTLS_MPI_INTERRUPT_LEVEL=0
|
||||||
CONFIG_MBEDTLS_HARDWARE_SHA=y
|
CONFIG_MBEDTLS_HARDWARE_SHA=y
|
||||||
CONFIG_MBEDTLS_HARDWARE_ECC=y
|
|
||||||
CONFIG_MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK=y
|
|
||||||
CONFIG_MBEDTLS_ROM_MD5=y
|
CONFIG_MBEDTLS_ROM_MD5=y
|
||||||
# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
|
# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
|
||||||
# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
|
# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
|
||||||
@ -1644,7 +1500,7 @@ CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53"
|
|||||||
|
|
||||||
CONFIG_OPENTHREAD_XTAL_ACCURACY=130
|
CONFIG_OPENTHREAD_XTAL_ACCURACY=130
|
||||||
# CONFIG_OPENTHREAD_SPINEL_ONLY is not set
|
# CONFIG_OPENTHREAD_SPINEL_ONLY is not set
|
||||||
# CONFIG_OPENTHREAD_RX_ON_WHEN_IDLE is not set
|
CONFIG_OPENTHREAD_RX_ON_WHEN_IDLE=y
|
||||||
|
|
||||||
#
|
#
|
||||||
# Thread Address Query Config
|
# Thread Address Query Config
|
||||||
@ -1673,9 +1529,9 @@ CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
|
|||||||
#
|
#
|
||||||
# MMU Config
|
# MMU Config
|
||||||
#
|
#
|
||||||
CONFIG_MMU_PAGE_SIZE_32KB=y
|
CONFIG_MMU_PAGE_SIZE_64KB=y
|
||||||
CONFIG_MMU_PAGE_MODE="32KB"
|
CONFIG_MMU_PAGE_MODE="64KB"
|
||||||
CONFIG_MMU_PAGE_SIZE=0x8000
|
CONFIG_MMU_PAGE_SIZE=0x10000
|
||||||
# end of MMU Config
|
# end of MMU Config
|
||||||
|
|
||||||
#
|
#
|
||||||
@ -1696,6 +1552,8 @@ CONFIG_SPI_FLASH_BROWNOUT_RESET=y
|
|||||||
#
|
#
|
||||||
# Features here require specific hardware (READ DOCS FIRST!)
|
# Features here require specific hardware (READ DOCS FIRST!)
|
||||||
#
|
#
|
||||||
|
CONFIG_SPI_FLASH_SUSPEND_QVL_SUPPORTED=y
|
||||||
|
# CONFIG_SPI_FLASH_AUTO_SUSPEND is not set
|
||||||
# end of Optional and Experimental Features (READ DOCS FIRST)
|
# end of Optional and Experimental Features (READ DOCS FIRST)
|
||||||
# end of Main Flash configuration
|
# end of Main Flash configuration
|
||||||
|
|
||||||
@ -1722,12 +1580,18 @@ CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
|
|||||||
# Auto-detect flash chips
|
# Auto-detect flash chips
|
||||||
#
|
#
|
||||||
CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
|
CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
|
||||||
# CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP is not set
|
CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y
|
||||||
# CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP is not set
|
CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y
|
||||||
# CONFIG_SPI_FLASH_SUPPORT_GD_CHIP is not set
|
CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y
|
||||||
# CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP is not set
|
CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y
|
||||||
# CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP is not set
|
CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y
|
||||||
# CONFIG_SPI_FLASH_SUPPORT_TH_CHIP is not set
|
CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y
|
||||||
|
CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
|
||||||
|
CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
|
||||||
|
CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
|
||||||
|
CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y
|
||||||
|
CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y
|
||||||
|
CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y
|
||||||
# end of Auto-detect flash chips
|
# end of Auto-detect flash chips
|
||||||
|
|
||||||
CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y
|
CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y
|
||||||
@ -1782,12 +1646,6 @@ CONFIG_WS_BUFFER_SIZE=1024
|
|||||||
# end of Websocket
|
# end of Websocket
|
||||||
# end of TCP Transport
|
# end of TCP Transport
|
||||||
|
|
||||||
#
|
|
||||||
# Ultra Low Power (ULP) Co-processor
|
|
||||||
#
|
|
||||||
# CONFIG_ULP_COPROC_ENABLED is not set
|
|
||||||
# end of Ultra Low Power (ULP) Co-processor
|
|
||||||
|
|
||||||
#
|
#
|
||||||
# Unity unit testing library
|
# Unity unit testing library
|
||||||
#
|
#
|
||||||
@ -1880,10 +1738,6 @@ CONFIG_STACK_CHECK_NONE=y
|
|||||||
# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
|
# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
|
||||||
CONFIG_ESP32_APPTRACE_DEST_NONE=y
|
CONFIG_ESP32_APPTRACE_DEST_NONE=y
|
||||||
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
|
CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
|
||||||
# CONFIG_MCPWM_ISR_IN_IRAM is not set
|
|
||||||
CONFIG_SW_COEXIST_ENABLE=y
|
|
||||||
CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE=y
|
|
||||||
CONFIG_ESP_WIFI_SW_COEXIST_ENABLE=y
|
|
||||||
# CONFIG_EXTERNAL_COEX_ENABLE is not set
|
# CONFIG_EXTERNAL_COEX_ENABLE is not set
|
||||||
# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
|
# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
|
||||||
# CONFIG_EVENT_LOOP_PROFILING is not set
|
# CONFIG_EVENT_LOOP_PROFILING is not set
|
||||||
@ -1893,6 +1747,12 @@ CONFIG_GDBSTUB_SUPPORT_TASKS=y
|
|||||||
CONFIG_GDBSTUB_MAX_TASKS=32
|
CONFIG_GDBSTUB_MAX_TASKS=32
|
||||||
# CONFIG_OTA_ALLOW_HTTP is not set
|
# CONFIG_OTA_ALLOW_HTTP is not set
|
||||||
# CONFIG_ESP_SYSTEM_PD_FLASH is not set
|
# CONFIG_ESP_SYSTEM_PD_FLASH is not set
|
||||||
|
CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y
|
||||||
|
CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y
|
||||||
|
# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set
|
||||||
|
# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set
|
||||||
|
# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set
|
||||||
|
CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024
|
||||||
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
|
CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
|
||||||
# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
|
# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
|
||||||
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
|
CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
|
||||||
@ -1900,6 +1760,11 @@ CONFIG_ESP32_PHY_MAX_TX_POWER=20
|
|||||||
# CONFIG_REDUCE_PHY_TX_POWER is not set
|
# CONFIG_REDUCE_PHY_TX_POWER is not set
|
||||||
# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
|
# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
|
||||||
CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y
|
CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y
|
||||||
|
# CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 is not set
|
||||||
|
CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y
|
||||||
|
CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160
|
||||||
|
CONFIG_ESP32C3_MEMPROT_FEATURE=y
|
||||||
|
CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK=y
|
||||||
CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
|
CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
|
||||||
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
|
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
|
||||||
CONFIG_MAIN_TASK_STACK_SIZE=3584
|
CONFIG_MAIN_TASK_STACK_SIZE=3584
|
||||||
@ -1918,14 +1783,24 @@ CONFIG_ESP_TASK_WDT=y
|
|||||||
CONFIG_TASK_WDT_TIMEOUT_S=5
|
CONFIG_TASK_WDT_TIMEOUT_S=5
|
||||||
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
|
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
|
||||||
# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
|
# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
|
||||||
|
CONFIG_ESP32C3_DEBUG_OCDAWARE=y
|
||||||
CONFIG_BROWNOUT_DET=y
|
CONFIG_BROWNOUT_DET=y
|
||||||
|
CONFIG_ESP32C3_BROWNOUT_DET=y
|
||||||
|
CONFIG_ESP32C3_BROWNOUT_DET=y
|
||||||
CONFIG_BROWNOUT_DET_LVL_SEL_7=y
|
CONFIG_BROWNOUT_DET_LVL_SEL_7=y
|
||||||
|
CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y
|
||||||
# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
|
# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
|
||||||
|
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set
|
||||||
# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
|
# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
|
||||||
|
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set
|
||||||
# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
|
# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
|
||||||
|
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set
|
||||||
# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
|
# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
|
||||||
|
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set
|
||||||
# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
|
# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
|
||||||
|
# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set
|
||||||
CONFIG_BROWNOUT_DET_LVL=7
|
CONFIG_BROWNOUT_DET_LVL=7
|
||||||
|
CONFIG_ESP32C3_BROWNOUT_DET_LVL=7
|
||||||
CONFIG_IPC_TASK_STACK_SIZE=1024
|
CONFIG_IPC_TASK_STACK_SIZE=1024
|
||||||
CONFIG_TIMER_TASK_STACK_SIZE=3584
|
CONFIG_TIMER_TASK_STACK_SIZE=3584
|
||||||
CONFIG_ESP32_WIFI_ENABLED=y
|
CONFIG_ESP32_WIFI_ENABLED=y
|
||||||
@ -1990,6 +1865,10 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
|
|||||||
# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
|
# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
|
||||||
CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
|
CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
|
||||||
# CONFIG_PPP_SUPPORT is not set
|
# CONFIG_PPP_SUPPORT is not set
|
||||||
|
CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y
|
||||||
|
# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set
|
||||||
|
# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set
|
||||||
|
# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set
|
||||||
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
|
CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
|
||||||
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
|
CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
|
||||||
CONFIG_ESP32_PTHREAD_STACK_MIN=768
|
CONFIG_ESP32_PTHREAD_STACK_MIN=768
|
||||||
|
|||||||
2004
rx_esp32/sdkconfig.esp32c6
Normal file
2004
rx_esp32/sdkconfig.esp32c6
Normal file
File diff suppressed because it is too large
Load Diff
@ -142,7 +142,7 @@ void app_main() {
|
|||||||
{
|
{
|
||||||
MainState = STATE_IDEL;
|
MainState = STATE_IDEL;
|
||||||
}
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
|
||||||
case STATE_IDEL:
|
case STATE_IDEL:
|
||||||
|
|||||||
@ -9,12 +9,12 @@
|
|||||||
#define SERVO_LEDC_TIMER LEDC_TIMER_0
|
#define SERVO_LEDC_TIMER LEDC_TIMER_0
|
||||||
#define SERVO_LEDC_MODE LEDC_LOW_SPEED_MODE
|
#define SERVO_LEDC_MODE LEDC_LOW_SPEED_MODE
|
||||||
#define SERVO_LEDC_CHANNEL LEDC_CHANNEL_0
|
#define SERVO_LEDC_CHANNEL LEDC_CHANNEL_0
|
||||||
#define SERVO_LEDC_DUTY_RES LEDC_TIMER_20_BIT // Set duty resolution to 13 bits
|
#define SERVO_LEDC_DUTY_RES LEDC_TIMER_13_BIT // Set duty resolution to 13 bits
|
||||||
// #define SERVO_DUTY_MIN ( 26214) // 2**20 * ( 500/20000) // 500us of the 20ms
|
// #define SERVO_DUTY_MIN ( 205) // 2**13 * ( 500/20000) // 500us of the 20ms
|
||||||
#define SERVO_DUTY_MIN ( 52429) // 2**20 * (1000/20000) // 1000us of the 20ms
|
#define SERVO_DUTY_MIN ( 410) // 2**13 * (1000/20000) // 1000us of the 20ms
|
||||||
#define SERVO_DUTY_MAX (104858) // 2**20 * (2000/20000) // 2000us of the 20ms
|
#define SERVO_DUTY_MAX ( 819) // 2**13 * (2000/20000) // 2000us of the 20ms
|
||||||
// #define SERVO_DUTY_MAX (131072) // 2**20 * (2500/20000) // 2500us of the 20ms
|
// #define SERVO_DUTY_MAX (1024) // 2**13 * (2500/20000) // 2500us of the 20ms
|
||||||
#define SERVO_DUTY_DEFUALT ( 78643) // 2**20 * (1500/20000) // 2500us of the 20ms
|
#define SERVO_DUTY_DEFUALT ( 614) // 2**13 * (1500/20000) // 2500us of the 20ms
|
||||||
|
|
||||||
#define SERVO_DUTY_DIFF (SERVO_DUTY_MAX - SERVO_DUTY_MIN)
|
#define SERVO_DUTY_DIFF (SERVO_DUTY_MAX - SERVO_DUTY_MIN)
|
||||||
|
|
||||||
@ -37,7 +37,7 @@ void servo_init(void)
|
|||||||
{
|
{
|
||||||
// Prepare and then apply the LEDC PWM timer configuration
|
// Prepare and then apply the LEDC PWM timer configuration
|
||||||
ledc_timer_config_t ledc_timer = {
|
ledc_timer_config_t ledc_timer = {
|
||||||
.speed_mode = LEDC_LOW_SPEED_MODE,
|
.speed_mode = SERVO_LEDC_MODE,
|
||||||
.timer_num = SERVO_LEDC_TIMER,
|
.timer_num = SERVO_LEDC_TIMER,
|
||||||
.duty_resolution = SERVO_LEDC_DUTY_RES,
|
.duty_resolution = SERVO_LEDC_DUTY_RES,
|
||||||
.freq_hz = 50, // 20ms period
|
.freq_hz = 50, // 20ms period
|
||||||
@ -49,7 +49,7 @@ void servo_init(void)
|
|||||||
{
|
{
|
||||||
// Prepare and then apply the LEDC PWM channel configuration
|
// Prepare and then apply the LEDC PWM channel configuration
|
||||||
ledc_channel_config_t ledc_channel = {
|
ledc_channel_config_t ledc_channel = {
|
||||||
.speed_mode = LEDC_LOW_SPEED_MODE,
|
.speed_mode = SERVO_LEDC_MODE,
|
||||||
.channel = Server_chs[i].channel,
|
.channel = Server_chs[i].channel,
|
||||||
.timer_sel = SERVO_LEDC_TIMER,
|
.timer_sel = SERVO_LEDC_TIMER,
|
||||||
.intr_type = LEDC_INTR_DISABLE,
|
.intr_type = LEDC_INTR_DISABLE,
|
||||||
@ -63,10 +63,10 @@ void servo_init(void)
|
|||||||
}
|
}
|
||||||
void servo_deinit(void)
|
void servo_deinit(void)
|
||||||
{
|
{
|
||||||
ledc_timer_pause(LEDC_LOW_SPEED_MODE, SERVO_LEDC_TIMER);
|
ledc_timer_pause(SERVO_LEDC_MODE, SERVO_LEDC_TIMER);
|
||||||
for (int i = sizeof(Server_chs)/sizeof(ServoCh_t)-1; i > 0; i--)
|
for (int i = sizeof(Server_chs)/sizeof(ServoCh_t)-1; i > 0; i--)
|
||||||
{
|
{
|
||||||
ledc_stop(LEDC_LOW_SPEED_MODE, Server_chs[i].channel, 0);
|
ledc_stop(SERVO_LEDC_MODE, Server_chs[i].channel, 0);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user