131 lines
4.2 KiB
Rust
131 lines
4.2 KiB
Rust
//! Interrupt types.
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use core::ops;
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#[allow(unused_imports)] // for intra-doc links only
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use crate::can::bx::{Can, Rx0};
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/// bxCAN interrupt sources.
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///
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/// These can be individually enabled and disabled in the bxCAN peripheral. Note that the bxCAN
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/// peripheral only exposes 4 interrupts to the microcontroller:
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///
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/// * TX
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/// * RX FIFO 1
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/// * RX FIFO 2
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/// * SCE (Status Change Error)
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///
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/// This means that some of the interrupts listed here will result in the same interrupt handler
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/// being invoked.
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Interrupt {
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/// Fires the **TX** interrupt when one of the transmit mailboxes returns to empty state.
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///
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/// This usually happens because its message was either transmitted successfully, or
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/// transmission was aborted successfully.
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///
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/// The interrupt handler must clear the interrupt condition by calling
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/// [`Can::clear_request_completed_flag`] or [`Can::clear_tx_interrupt`].
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TransmitMailboxEmpty = 1 << 0,
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/// Fires the **RX FIFO 0** interrupt when FIFO 0 holds a message.
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///
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/// The interrupt handler must clear the interrupt condition by receiving all messages from the
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/// FIFO by calling [`Can::receive`] or [`Rx0::receive`].
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Fifo0MessagePending = 1 << 1,
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/// Fires the **RX FIFO 0** interrupt when FIFO 0 holds 3 incoming messages.
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///
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/// The interrupt handler must clear the interrupt condition by receiving at least one message
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/// from the FIFO (making it no longer "full"). This can be done by calling [`Can::receive`] or
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/// [`Rx0::receive`].
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Fifo0Full = 1 << 2,
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/// Fires the **RX FIFO 0** interrupt when FIFO 0 drops an incoming message.
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///
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/// The interrupt handler must clear the interrupt condition by calling [`Can::receive`] or
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/// [`Rx0::receive`] (which will return an error).
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Fifo0Overrun = 1 << 3,
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/// Fires the **RX FIFO 1** interrupt when FIFO 1 holds a message.
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///
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/// Behavior is otherwise identical to [`Self::Fifo0MessagePending`].
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Fifo1MessagePending = 1 << 4,
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/// Fires the **RX FIFO 1** interrupt when FIFO 1 holds 3 incoming messages.
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///
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/// Behavior is otherwise identical to [`Self::Fifo0Full`].
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Fifo1Full = 1 << 5,
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/// Fires the **RX FIFO 1** interrupt when FIFO 1 drops an incoming message.
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///
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/// Behavior is otherwise identical to [`Self::Fifo0Overrun`].
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Fifo1Overrun = 1 << 6,
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Error = 1 << 15,
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/// Fires the **SCE** interrupt when an incoming CAN frame is detected while the peripheral is
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/// in sleep mode.
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///
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/// The interrupt handler must clear the interrupt condition by calling
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/// [`Can::clear_wakeup_interrupt`].
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Wakeup = 1 << 16,
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/// Fires the **SCE** interrupt when the peripheral enters sleep mode.
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///
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/// The interrupt handler must clear the interrupt condition by calling
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/// [`Can::clear_sleep_interrupt`].
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Sleep = 1 << 17,
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}
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bitflags::bitflags! {
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/// A set of bxCAN interrupts.
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pub struct Interrupts: u32 {
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const TRANSMIT_MAILBOX_EMPTY = 1 << 0;
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const FIFO0_MESSAGE_PENDING = 1 << 1;
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const FIFO0_FULL = 1 << 2;
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const FIFO0_OVERRUN = 1 << 3;
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const FIFO1_MESSAGE_PENDING = 1 << 4;
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const FIFO1_FULL = 1 << 5;
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const FIFO1_OVERRUN = 1 << 6;
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const ERROR = 1 << 15;
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const WAKEUP = 1 << 16;
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const SLEEP = 1 << 17;
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}
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}
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impl From<Interrupt> for Interrupts {
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#[inline]
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fn from(i: Interrupt) -> Self {
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Self::from_bits_truncate(i as u32)
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}
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}
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/// Adds an interrupt to the interrupt set.
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impl ops::BitOrAssign<Interrupt> for Interrupts {
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#[inline]
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fn bitor_assign(&mut self, rhs: Interrupt) {
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*self |= Self::from(rhs);
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn interrupt_flags() {
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assert_eq!(Interrupts::from(Interrupt::Sleep), Interrupts::SLEEP);
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assert_eq!(
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Interrupts::from(Interrupt::TransmitMailboxEmpty),
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Interrupts::TRANSMIT_MAILBOX_EMPTY
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);
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let mut ints = Interrupts::FIFO0_FULL;
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ints |= Interrupt::Fifo1Full;
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assert_eq!(ints, Interrupts::FIFO0_FULL | Interrupts::FIFO1_FULL);
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}
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}
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