00ff1409cd
The half transfer irq needs to be enabled in order for the hardware to notify the waker when the transfer is at half. This is needed to ensure no overuns occur when using `ReadableDmaRingBuffer`'s `read_exact`. Otherwise we are only notified when the DMA has completed its cycle and is on its way to start overwriting the data. The docs in the dma_bdma buf module also seem to imply that the half transfer irq must be enabled for proper operation. The only consumers of the `ReadableDmaRingBuffer` api are the sai module and the `RingBufferedUartRx`. The former enables the irq manually when constructing the transfer options while the latter does not. This may also be the cause for #1441.
1012 lines
31 KiB
Rust
1012 lines
31 KiB
Rust
use core::future::{poll_fn, Future};
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use core::pin::Pin;
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use core::sync::atomic::{fence, AtomicUsize, Ordering};
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use core::task::{Context, Poll, Waker};
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer};
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use super::word::{Word, WordSize};
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use super::{AnyChannel, Channel, Dir, Request, STATE};
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use crate::interrupt::typelevel::Interrupt;
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use crate::{interrupt, pac};
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pub(crate) struct ChannelInfo {
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pub(crate) dma: DmaInfo,
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pub(crate) num: usize,
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#[cfg(dmamux)]
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pub(crate) dmamux: super::DmamuxInfo,
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}
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#[derive(Clone, Copy)]
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pub(crate) enum DmaInfo {
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#[cfg(dma)]
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Dma(pac::dma::Dma),
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#[cfg(bdma)]
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Bdma(pac::bdma::Dma),
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}
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/// DMA transfer options.
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub struct TransferOptions {
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/// Peripheral burst transfer configuration
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#[cfg(dma)]
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pub pburst: Burst,
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/// Memory burst transfer configuration
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#[cfg(dma)]
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pub mburst: Burst,
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/// Flow control configuration
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#[cfg(dma)]
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pub flow_ctrl: FlowControl,
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/// FIFO threshold for DMA FIFO mode. If none, direct mode is used.
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#[cfg(dma)]
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pub fifo_threshold: Option<FifoThreshold>,
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/// Request priority level
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pub priority: Priority,
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/// Enable circular DMA
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///
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/// Note:
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/// If you enable circular mode manually, you may want to build and `.await` the `Transfer` in a separate task.
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/// Since DMA in circular mode need manually stop, `.await` in current task would block the task forever.
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pub circular: bool,
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/// Enable half transfer interrupt
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pub half_transfer_ir: bool,
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/// Enable transfer complete interrupt
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pub complete_transfer_ir: bool,
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}
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impl Default for TransferOptions {
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fn default() -> Self {
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Self {
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#[cfg(dma)]
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pburst: Burst::Single,
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#[cfg(dma)]
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mburst: Burst::Single,
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#[cfg(dma)]
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flow_ctrl: FlowControl::Dma,
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#[cfg(dma)]
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fifo_threshold: None,
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priority: Priority::VeryHigh,
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circular: false,
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half_transfer_ir: false,
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complete_transfer_ir: true,
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}
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}
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}
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/// DMA request priority
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Priority {
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/// Low Priority
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Low,
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/// Medium Priority
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Medium,
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/// High Priority
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High,
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/// Very High Priority
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VeryHigh,
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}
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#[cfg(dma)]
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impl From<Priority> for pac::dma::vals::Pl {
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fn from(value: Priority) -> Self {
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match value {
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Priority::Low => pac::dma::vals::Pl::LOW,
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Priority::Medium => pac::dma::vals::Pl::MEDIUM,
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Priority::High => pac::dma::vals::Pl::HIGH,
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Priority::VeryHigh => pac::dma::vals::Pl::VERYHIGH,
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}
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}
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}
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#[cfg(bdma)]
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impl From<Priority> for pac::bdma::vals::Pl {
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fn from(value: Priority) -> Self {
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match value {
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Priority::Low => pac::bdma::vals::Pl::LOW,
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Priority::Medium => pac::bdma::vals::Pl::MEDIUM,
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Priority::High => pac::bdma::vals::Pl::HIGH,
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Priority::VeryHigh => pac::bdma::vals::Pl::VERYHIGH,
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}
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}
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}
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#[cfg(dma)]
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pub use dma_only::*;
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#[cfg(dma)]
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mod dma_only {
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use pac::dma::vals;
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use super::*;
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impl From<WordSize> for vals::Size {
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fn from(raw: WordSize) -> Self {
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match raw {
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WordSize::OneByte => Self::BITS8,
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WordSize::TwoBytes => Self::BITS16,
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WordSize::FourBytes => Self::BITS32,
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}
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}
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}
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impl From<Dir> for vals::Dir {
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fn from(raw: Dir) -> Self {
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match raw {
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Dir::MemoryToPeripheral => Self::MEMORYTOPERIPHERAL,
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Dir::PeripheralToMemory => Self::PERIPHERALTOMEMORY,
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}
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}
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}
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/// DMA transfer burst setting.
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Burst {
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/// Single transfer
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Single,
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/// Incremental burst of 4 beats
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Incr4,
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/// Incremental burst of 8 beats
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Incr8,
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/// Incremental burst of 16 beats
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Incr16,
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}
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impl From<Burst> for vals::Burst {
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fn from(burst: Burst) -> Self {
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match burst {
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Burst::Single => vals::Burst::SINGLE,
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Burst::Incr4 => vals::Burst::INCR4,
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Burst::Incr8 => vals::Burst::INCR8,
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Burst::Incr16 => vals::Burst::INCR16,
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}
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}
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}
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/// DMA flow control setting.
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum FlowControl {
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/// Flow control by DMA
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Dma,
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/// Flow control by peripheral
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Peripheral,
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}
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impl From<FlowControl> for vals::Pfctrl {
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fn from(flow: FlowControl) -> Self {
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match flow {
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FlowControl::Dma => vals::Pfctrl::DMA,
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FlowControl::Peripheral => vals::Pfctrl::PERIPHERAL,
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}
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}
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}
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/// DMA FIFO threshold.
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum FifoThreshold {
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/// 1/4 full FIFO
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Quarter,
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/// 1/2 full FIFO
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Half,
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/// 3/4 full FIFO
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ThreeQuarters,
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/// Full FIFO
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Full,
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}
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impl From<FifoThreshold> for vals::Fth {
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fn from(value: FifoThreshold) -> Self {
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match value {
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FifoThreshold::Quarter => vals::Fth::QUARTER,
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FifoThreshold::Half => vals::Fth::HALF,
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FifoThreshold::ThreeQuarters => vals::Fth::THREEQUARTERS,
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FifoThreshold::Full => vals::Fth::FULL,
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}
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}
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}
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}
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#[cfg(bdma)]
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mod bdma_only {
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use pac::bdma::vals;
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use super::*;
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impl From<WordSize> for vals::Size {
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fn from(raw: WordSize) -> Self {
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match raw {
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WordSize::OneByte => Self::BITS8,
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WordSize::TwoBytes => Self::BITS16,
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WordSize::FourBytes => Self::BITS32,
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}
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}
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}
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impl From<Dir> for vals::Dir {
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fn from(raw: Dir) -> Self {
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match raw {
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Dir::MemoryToPeripheral => Self::FROMMEMORY,
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Dir::PeripheralToMemory => Self::FROMPERIPHERAL,
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}
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}
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}
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}
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pub(crate) struct ChannelState {
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waker: AtomicWaker,
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complete_count: AtomicUsize,
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}
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impl ChannelState {
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pub(crate) const NEW: Self = Self {
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waker: AtomicWaker::new(),
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complete_count: AtomicUsize::new(0),
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};
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}
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/// safety: must be called only once
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pub(crate) unsafe fn init(
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cs: critical_section::CriticalSection,
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#[cfg(dma)] dma_priority: interrupt::Priority,
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#[cfg(bdma)] bdma_priority: interrupt::Priority,
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) {
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foreach_interrupt! {
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($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
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crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, dma_priority);
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crate::interrupt::typelevel::$irq::enable();
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};
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($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
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crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, bdma_priority);
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crate::interrupt::typelevel::$irq::enable();
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};
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}
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crate::_generated::init_dma();
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crate::_generated::init_bdma();
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}
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impl AnyChannel {
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/// Safety: Must be called with a matching set of parameters for a valid dma channel
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pub(crate) unsafe fn on_irq(&self) {
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let info = self.info();
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let state = &STATE[self.id as usize];
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match self.info().dma {
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#[cfg(dma)]
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DmaInfo::Dma(r) => {
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let cr = r.st(info.num).cr();
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let isr = r.isr(info.num / 4).read();
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if isr.teif(info.num % 4) {
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panic!("DMA: error on DMA@{:08x} channel {}", r.as_ptr() as u32, info.num);
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}
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if isr.htif(info.num % 4) && cr.read().htie() {
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// Acknowledge half transfer complete interrupt
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r.ifcr(info.num / 4).write(|w| w.set_htif(info.num % 4, true));
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} else if isr.tcif(info.num % 4) && cr.read().tcie() {
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// Acknowledge transfer complete interrupt
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r.ifcr(info.num / 4).write(|w| w.set_tcif(info.num % 4, true));
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state.complete_count.fetch_add(1, Ordering::Release);
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} else {
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return;
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}
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state.waker.wake();
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}
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#[cfg(bdma)]
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DmaInfo::Bdma(r) => {
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let isr = r.isr().read();
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let cr = r.ch(info.num).cr();
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if isr.teif(info.num) {
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panic!("DMA: error on BDMA@{:08x} channel {}", r.as_ptr() as u32, info.num);
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}
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if isr.htif(info.num) && cr.read().htie() {
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// Acknowledge half transfer complete interrupt
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r.ifcr().write(|w| w.set_htif(info.num, true));
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} else if isr.tcif(info.num) && cr.read().tcie() {
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// Acknowledge transfer complete interrupt
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r.ifcr().write(|w| w.set_tcif(info.num, true));
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#[cfg(not(armv6m))]
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state.complete_count.fetch_add(1, Ordering::Release);
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#[cfg(armv6m)]
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critical_section::with(|_| {
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let x = state.complete_count.load(Ordering::Relaxed);
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state.complete_count.store(x + 1, Ordering::Release);
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})
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} else {
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return;
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}
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state.waker.wake();
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}
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}
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}
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unsafe fn configure(
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&self,
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_request: Request,
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dir: Dir,
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peri_addr: *const u32,
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mem_addr: *mut u32,
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mem_len: usize,
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incr_mem: bool,
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data_size: WordSize,
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options: TransferOptions,
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) {
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let info = self.info();
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&info.dmamux, _request);
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assert!(mem_len > 0 && mem_len <= 0xFFFF);
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|
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match self.info().dma {
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#[cfg(dma)]
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DmaInfo::Dma(r) => {
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let ch = r.st(info.num);
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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self.clear_irqs();
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ch.par().write_value(peri_addr as u32);
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ch.m0ar().write_value(mem_addr as u32);
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ch.ndtr().write_value(pac::dma::regs::Ndtr(mem_len as _));
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ch.fcr().write(|w| {
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if let Some(fth) = options.fifo_threshold {
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// FIFO mode
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w.set_dmdis(pac::dma::vals::Dmdis::DISABLED);
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w.set_fth(fth.into());
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} else {
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// Direct mode
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w.set_dmdis(pac::dma::vals::Dmdis::ENABLED);
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}
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});
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ch.cr().write(|w| {
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w.set_dir(dir.into());
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w.set_msize(data_size.into());
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w.set_psize(data_size.into());
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w.set_pl(options.priority.into());
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w.set_minc(incr_mem);
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w.set_pinc(false);
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w.set_teie(true);
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w.set_htie(options.half_transfer_ir);
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w.set_tcie(options.complete_transfer_ir);
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w.set_circ(options.circular);
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#[cfg(dma_v1)]
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w.set_trbuff(true);
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#[cfg(dma_v2)]
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w.set_chsel(_request);
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w.set_pburst(options.pburst.into());
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w.set_mburst(options.mburst.into());
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w.set_pfctrl(options.flow_ctrl.into());
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w.set_en(false); // don't start yet
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});
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}
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#[cfg(bdma)]
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DmaInfo::Bdma(r) => {
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#[cfg(bdma_v2)]
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critical_section::with(|_| r.cselr().modify(|w| w.set_cs(info.num, _request)));
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|
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let state: &ChannelState = &STATE[self.id as usize];
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let ch = r.ch(info.num);
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state.complete_count.store(0, Ordering::Release);
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self.clear_irqs();
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|
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ch.par().write_value(peri_addr as u32);
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ch.mar().write_value(mem_addr as u32);
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ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
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ch.cr().write(|w| {
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w.set_psize(data_size.into());
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w.set_msize(data_size.into());
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w.set_minc(incr_mem);
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w.set_dir(dir.into());
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w.set_teie(true);
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w.set_tcie(options.complete_transfer_ir);
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w.set_htie(options.half_transfer_ir);
|
|
w.set_circ(options.circular);
|
|
w.set_pl(options.priority.into());
|
|
w.set_en(false); // don't start yet
|
|
});
|
|
}
|
|
}
|
|
}
|
|
|
|
fn start(&self) {
|
|
let info = self.info();
|
|
match self.info().dma {
|
|
#[cfg(dma)]
|
|
DmaInfo::Dma(r) => {
|
|
let ch = r.st(info.num);
|
|
ch.cr().modify(|w| w.set_en(true))
|
|
}
|
|
#[cfg(bdma)]
|
|
DmaInfo::Bdma(r) => {
|
|
let ch = r.ch(info.num);
|
|
ch.cr().modify(|w| w.set_en(true));
|
|
}
|
|
}
|
|
}
|
|
|
|
fn clear_irqs(&self) {
|
|
let info = self.info();
|
|
match self.info().dma {
|
|
#[cfg(dma)]
|
|
DmaInfo::Dma(r) => {
|
|
let isrn = info.num / 4;
|
|
let isrbit = info.num % 4;
|
|
|
|
r.ifcr(isrn).write(|w| {
|
|
w.set_htif(isrbit, true);
|
|
w.set_tcif(isrbit, true);
|
|
w.set_teif(isrbit, true);
|
|
});
|
|
}
|
|
#[cfg(bdma)]
|
|
DmaInfo::Bdma(r) => {
|
|
r.ifcr().write(|w| {
|
|
w.set_htif(info.num, true);
|
|
w.set_tcif(info.num, true);
|
|
w.set_teif(info.num, true);
|
|
});
|
|
}
|
|
}
|
|
}
|
|
|
|
fn request_stop(&self) {
|
|
let info = self.info();
|
|
match self.info().dma {
|
|
#[cfg(dma)]
|
|
DmaInfo::Dma(r) => {
|
|
// Disable the channel. Keep the IEs enabled so the irqs still fire.
|
|
r.st(info.num).cr().write(|w| {
|
|
w.set_teie(true);
|
|
w.set_tcie(true);
|
|
});
|
|
}
|
|
#[cfg(bdma)]
|
|
DmaInfo::Bdma(r) => {
|
|
// Disable the channel. Keep the IEs enabled so the irqs still fire.
|
|
r.ch(info.num).cr().write(|w| {
|
|
w.set_teie(true);
|
|
w.set_tcie(true);
|
|
});
|
|
}
|
|
}
|
|
}
|
|
|
|
fn is_running(&self) -> bool {
|
|
let info = self.info();
|
|
match self.info().dma {
|
|
#[cfg(dma)]
|
|
DmaInfo::Dma(r) => r.st(info.num).cr().read().en(),
|
|
#[cfg(bdma)]
|
|
DmaInfo::Bdma(r) => {
|
|
let state: &ChannelState = &STATE[self.id as usize];
|
|
let ch = r.ch(info.num);
|
|
let en = ch.cr().read().en();
|
|
let circular = ch.cr().read().circ();
|
|
let tcif = state.complete_count.load(Ordering::Acquire) != 0;
|
|
en && (circular || !tcif)
|
|
}
|
|
}
|
|
}
|
|
|
|
fn get_remaining_transfers(&self) -> u16 {
|
|
let info = self.info();
|
|
match self.info().dma {
|
|
#[cfg(dma)]
|
|
DmaInfo::Dma(r) => r.st(info.num).ndtr().read().ndt(),
|
|
#[cfg(bdma)]
|
|
DmaInfo::Bdma(r) => r.ch(info.num).ndtr().read().ndt(),
|
|
}
|
|
}
|
|
|
|
fn disable_circular_mode(&self) {
|
|
let info = self.info();
|
|
match self.info().dma {
|
|
#[cfg(dma)]
|
|
DmaInfo::Dma(regs) => regs.st(info.num).cr().modify(|w| {
|
|
w.set_circ(false);
|
|
}),
|
|
#[cfg(bdma)]
|
|
DmaInfo::Bdma(regs) => regs.ch(info.num).cr().modify(|w| {
|
|
w.set_circ(false);
|
|
}),
|
|
}
|
|
}
|
|
|
|
fn poll_stop(&self) -> Poll<()> {
|
|
use core::sync::atomic::compiler_fence;
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
if !self.is_running() {
|
|
Poll::Ready(())
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
}
|
|
}
|
|
|
|
/// DMA transfer.
|
|
#[must_use = "futures do nothing unless you `.await` or poll them"]
|
|
pub struct Transfer<'a> {
|
|
channel: PeripheralRef<'a, AnyChannel>,
|
|
}
|
|
|
|
impl<'a> Transfer<'a> {
|
|
/// Create a new read DMA transfer (peripheral to memory).
|
|
pub unsafe fn new_read<W: Word>(
|
|
channel: impl Peripheral<P = impl Channel> + 'a,
|
|
request: Request,
|
|
peri_addr: *mut W,
|
|
buf: &'a mut [W],
|
|
options: TransferOptions,
|
|
) -> Self {
|
|
Self::new_read_raw(channel, request, peri_addr, buf, options)
|
|
}
|
|
|
|
/// Create a new read DMA transfer (peripheral to memory), using raw pointers.
|
|
pub unsafe fn new_read_raw<W: Word>(
|
|
channel: impl Peripheral<P = impl Channel> + 'a,
|
|
request: Request,
|
|
peri_addr: *mut W,
|
|
buf: *mut [W],
|
|
options: TransferOptions,
|
|
) -> Self {
|
|
into_ref!(channel);
|
|
|
|
Self::new_inner(
|
|
channel.map_into(),
|
|
request,
|
|
Dir::PeripheralToMemory,
|
|
peri_addr as *const u32,
|
|
buf as *mut W as *mut u32,
|
|
buf.len(),
|
|
true,
|
|
W::size(),
|
|
options,
|
|
)
|
|
}
|
|
|
|
/// Create a new write DMA transfer (memory to peripheral).
|
|
pub unsafe fn new_write<W: Word>(
|
|
channel: impl Peripheral<P = impl Channel> + 'a,
|
|
request: Request,
|
|
buf: &'a [W],
|
|
peri_addr: *mut W,
|
|
options: TransferOptions,
|
|
) -> Self {
|
|
Self::new_write_raw(channel, request, buf, peri_addr, options)
|
|
}
|
|
|
|
/// Create a new write DMA transfer (memory to peripheral), using raw pointers.
|
|
pub unsafe fn new_write_raw<W: Word>(
|
|
channel: impl Peripheral<P = impl Channel> + 'a,
|
|
request: Request,
|
|
buf: *const [W],
|
|
peri_addr: *mut W,
|
|
options: TransferOptions,
|
|
) -> Self {
|
|
into_ref!(channel);
|
|
|
|
Self::new_inner(
|
|
channel.map_into(),
|
|
request,
|
|
Dir::MemoryToPeripheral,
|
|
peri_addr as *const u32,
|
|
buf as *const W as *mut u32,
|
|
buf.len(),
|
|
true,
|
|
W::size(),
|
|
options,
|
|
)
|
|
}
|
|
|
|
/// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
|
|
pub unsafe fn new_write_repeated<W: Word>(
|
|
channel: impl Peripheral<P = impl Channel> + 'a,
|
|
request: Request,
|
|
repeated: &'a W,
|
|
count: usize,
|
|
peri_addr: *mut W,
|
|
options: TransferOptions,
|
|
) -> Self {
|
|
into_ref!(channel);
|
|
|
|
Self::new_inner(
|
|
channel.map_into(),
|
|
request,
|
|
Dir::MemoryToPeripheral,
|
|
peri_addr as *const u32,
|
|
repeated as *const W as *mut u32,
|
|
count,
|
|
false,
|
|
W::size(),
|
|
options,
|
|
)
|
|
}
|
|
|
|
unsafe fn new_inner(
|
|
channel: PeripheralRef<'a, AnyChannel>,
|
|
_request: Request,
|
|
dir: Dir,
|
|
peri_addr: *const u32,
|
|
mem_addr: *mut u32,
|
|
mem_len: usize,
|
|
incr_mem: bool,
|
|
data_size: WordSize,
|
|
options: TransferOptions,
|
|
) -> Self {
|
|
assert!(mem_len > 0 && mem_len <= 0xFFFF);
|
|
|
|
channel.configure(
|
|
_request, dir, peri_addr, mem_addr, mem_len, incr_mem, data_size, options,
|
|
);
|
|
channel.start();
|
|
|
|
Self { channel }
|
|
}
|
|
|
|
/// Request the transfer to stop.
|
|
///
|
|
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
|
|
pub fn request_stop(&mut self) {
|
|
self.channel.request_stop()
|
|
}
|
|
|
|
/// Return whether this transfer is still running.
|
|
///
|
|
/// If this returns `false`, it can be because either the transfer finished, or
|
|
/// it was requested to stop early with [`request_stop`](Self::request_stop).
|
|
pub fn is_running(&mut self) -> bool {
|
|
self.channel.is_running()
|
|
}
|
|
|
|
/// Gets the total remaining transfers for the channel
|
|
/// Note: this will be zero for transfers that completed without cancellation.
|
|
pub fn get_remaining_transfers(&self) -> u16 {
|
|
self.channel.get_remaining_transfers()
|
|
}
|
|
|
|
/// Blocking wait until the transfer finishes.
|
|
pub fn blocking_wait(mut self) {
|
|
while self.is_running() {}
|
|
|
|
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
|
fence(Ordering::SeqCst);
|
|
|
|
core::mem::forget(self);
|
|
}
|
|
}
|
|
|
|
impl<'a> Drop for Transfer<'a> {
|
|
fn drop(&mut self) {
|
|
self.request_stop();
|
|
while self.is_running() {}
|
|
|
|
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
|
fence(Ordering::SeqCst);
|
|
}
|
|
}
|
|
|
|
impl<'a> Unpin for Transfer<'a> {}
|
|
impl<'a> Future for Transfer<'a> {
|
|
type Output = ();
|
|
fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
|
|
let state: &ChannelState = &STATE[self.channel.id as usize];
|
|
|
|
state.waker.register(cx.waker());
|
|
|
|
if self.is_running() {
|
|
Poll::Pending
|
|
} else {
|
|
Poll::Ready(())
|
|
}
|
|
}
|
|
}
|
|
|
|
// ==============================
|
|
|
|
struct DmaCtrlImpl<'a>(PeripheralRef<'a, AnyChannel>);
|
|
|
|
impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
|
|
fn get_remaining_transfers(&self) -> usize {
|
|
self.0.get_remaining_transfers() as _
|
|
}
|
|
|
|
fn get_complete_count(&self) -> usize {
|
|
STATE[self.0.id as usize].complete_count.load(Ordering::Acquire)
|
|
}
|
|
|
|
fn reset_complete_count(&mut self) -> usize {
|
|
let state = &STATE[self.0.id as usize];
|
|
#[cfg(not(armv6m))]
|
|
return state.complete_count.swap(0, Ordering::AcqRel);
|
|
#[cfg(armv6m)]
|
|
return critical_section::with(|_| {
|
|
let x = state.complete_count.load(Ordering::Acquire);
|
|
state.complete_count.store(0, Ordering::Release);
|
|
x
|
|
});
|
|
}
|
|
|
|
fn set_waker(&mut self, waker: &Waker) {
|
|
STATE[self.0.id as usize].waker.register(waker);
|
|
}
|
|
}
|
|
|
|
/// Ringbuffer for receiving data using DMA circular mode.
|
|
pub struct ReadableRingBuffer<'a, W: Word> {
|
|
channel: PeripheralRef<'a, AnyChannel>,
|
|
ringbuf: ReadableDmaRingBuffer<'a, W>,
|
|
}
|
|
|
|
impl<'a, W: Word> ReadableRingBuffer<'a, W> {
|
|
/// Create a new ring buffer.
|
|
pub unsafe fn new(
|
|
channel: impl Peripheral<P = impl Channel> + 'a,
|
|
_request: Request,
|
|
peri_addr: *mut W,
|
|
buffer: &'a mut [W],
|
|
mut options: TransferOptions,
|
|
) -> Self {
|
|
into_ref!(channel);
|
|
let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
|
|
|
|
let buffer_ptr = buffer.as_mut_ptr();
|
|
let len = buffer.len();
|
|
let dir = Dir::PeripheralToMemory;
|
|
let data_size = W::size();
|
|
|
|
options.complete_transfer_ir = true;
|
|
options.circular = true;
|
|
|
|
channel.configure(
|
|
_request,
|
|
dir,
|
|
peri_addr as *mut u32,
|
|
buffer_ptr as *mut u32,
|
|
len,
|
|
true,
|
|
data_size,
|
|
options,
|
|
);
|
|
|
|
Self {
|
|
channel,
|
|
ringbuf: ReadableDmaRingBuffer::new(buffer),
|
|
}
|
|
}
|
|
|
|
/// Start the ring buffer operation.
|
|
///
|
|
/// You must call this after creating it for it to work.
|
|
pub fn start(&mut self) {
|
|
self.channel.start()
|
|
}
|
|
|
|
/// Clear all data in the ring buffer.
|
|
pub fn clear(&mut self) {
|
|
self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
|
|
}
|
|
|
|
/// Read elements from the ring buffer
|
|
/// Return a tuple of the length read and the length remaining in the buffer
|
|
/// If not all of the elements were read, then there will be some elements in the buffer remaining
|
|
/// The length remaining is the capacity, ring_buf.len(), less the elements remaining after the read
|
|
/// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
|
|
pub fn read(&mut self, buf: &mut [W]) -> Result<(usize, usize), OverrunError> {
|
|
self.ringbuf.read(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
|
|
}
|
|
|
|
/// Read an exact number of elements from the ringbuffer.
|
|
///
|
|
/// Returns the remaining number of elements available for immediate reading.
|
|
/// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
|
|
///
|
|
/// Async/Wake Behavior:
|
|
/// The underlying DMA peripheral only can wake us when its buffer pointer has reached the halfway point,
|
|
/// and when it wraps around. This means that when called with a buffer of length 'M', when this
|
|
/// ring buffer was created with a buffer of size 'N':
|
|
/// - If M equals N/2 or N/2 divides evenly into M, this function will return every N/2 elements read on the DMA source.
|
|
/// - Otherwise, this function may need up to N/2 extra elements to arrive before returning.
|
|
pub async fn read_exact(&mut self, buffer: &mut [W]) -> Result<usize, OverrunError> {
|
|
self.ringbuf
|
|
.read_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
|
|
.await
|
|
}
|
|
|
|
/// The capacity of the ringbuffer
|
|
pub const fn capacity(&self) -> usize {
|
|
self.ringbuf.cap()
|
|
}
|
|
|
|
/// Set a waker to be woken when at least one byte is received.
|
|
pub fn set_waker(&mut self, waker: &Waker) {
|
|
DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
|
|
}
|
|
|
|
/// Request DMA to stop.
|
|
///
|
|
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
|
|
pub fn request_stop(&mut self) {
|
|
self.channel.request_stop()
|
|
}
|
|
|
|
/// Return whether DMA is still running.
|
|
///
|
|
/// If this returns `false`, it can be because either the transfer finished, or
|
|
/// it was requested to stop early with [`request_stop`](Self::request_stop).
|
|
pub fn is_running(&mut self) -> bool {
|
|
self.channel.is_running()
|
|
}
|
|
|
|
/// Stop the DMA transfer and await until the buffer is full.
|
|
///
|
|
/// This disables the DMA transfer's circular mode so that the transfer
|
|
/// stops when the buffer is full.
|
|
///
|
|
/// This is designed to be used with streaming input data such as the
|
|
/// I2S/SAI or ADC.
|
|
///
|
|
/// When using the UART, you probably want `request_stop()`.
|
|
pub async fn stop(&mut self) {
|
|
self.channel.disable_circular_mode();
|
|
//wait until cr.susp reads as true
|
|
poll_fn(|cx| {
|
|
self.set_waker(cx.waker());
|
|
self.channel.poll_stop()
|
|
})
|
|
.await
|
|
}
|
|
}
|
|
|
|
impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
|
|
fn drop(&mut self) {
|
|
self.request_stop();
|
|
while self.is_running() {}
|
|
|
|
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
|
fence(Ordering::SeqCst);
|
|
}
|
|
}
|
|
|
|
/// Ringbuffer for writing data using DMA circular mode.
|
|
pub struct WritableRingBuffer<'a, W: Word> {
|
|
channel: PeripheralRef<'a, AnyChannel>,
|
|
ringbuf: WritableDmaRingBuffer<'a, W>,
|
|
}
|
|
|
|
impl<'a, W: Word> WritableRingBuffer<'a, W> {
|
|
/// Create a new ring buffer.
|
|
pub unsafe fn new(
|
|
channel: impl Peripheral<P = impl Channel> + 'a,
|
|
_request: Request,
|
|
peri_addr: *mut W,
|
|
buffer: &'a mut [W],
|
|
mut options: TransferOptions,
|
|
) -> Self {
|
|
into_ref!(channel);
|
|
let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
|
|
|
|
let len = buffer.len();
|
|
let dir = Dir::MemoryToPeripheral;
|
|
let data_size = W::size();
|
|
let buffer_ptr = buffer.as_mut_ptr();
|
|
|
|
options.half_transfer_ir = true;
|
|
options.complete_transfer_ir = true;
|
|
options.circular = true;
|
|
|
|
channel.configure(
|
|
_request,
|
|
dir,
|
|
peri_addr as *mut u32,
|
|
buffer_ptr as *mut u32,
|
|
len,
|
|
true,
|
|
data_size,
|
|
options,
|
|
);
|
|
|
|
Self {
|
|
channel,
|
|
ringbuf: WritableDmaRingBuffer::new(buffer),
|
|
}
|
|
}
|
|
|
|
/// Start the ring buffer operation.
|
|
///
|
|
/// You must call this after creating it for it to work.
|
|
pub fn start(&mut self) {
|
|
self.channel.start()
|
|
}
|
|
|
|
/// Clear all data in the ring buffer.
|
|
pub fn clear(&mut self) {
|
|
self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
|
|
}
|
|
|
|
/// Write elements directly to the raw buffer.
|
|
/// This can be used to fill the buffer before starting the DMA transfer.
|
|
#[allow(dead_code)]
|
|
pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
|
|
self.ringbuf.write_immediate(buf)
|
|
}
|
|
|
|
/// Write elements from the ring buffer
|
|
/// Return a tuple of the length written and the length remaining in the buffer
|
|
pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
|
|
self.ringbuf.write(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
|
|
}
|
|
|
|
/// Write an exact number of elements to the ringbuffer.
|
|
pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
|
|
self.ringbuf
|
|
.write_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
|
|
.await
|
|
}
|
|
|
|
/// The capacity of the ringbuffer
|
|
pub const fn capacity(&self) -> usize {
|
|
self.ringbuf.cap()
|
|
}
|
|
|
|
/// Set a waker to be woken when at least one byte is received.
|
|
pub fn set_waker(&mut self, waker: &Waker) {
|
|
DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
|
|
}
|
|
|
|
/// Request DMA to stop.
|
|
///
|
|
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
|
|
pub fn request_stop(&mut self) {
|
|
self.channel.request_stop()
|
|
}
|
|
|
|
/// Return whether DMA is still running.
|
|
///
|
|
/// If this returns `false`, it can be because either the transfer finished, or
|
|
/// it was requested to stop early with [`request_stop`](Self::request_stop).
|
|
pub fn is_running(&mut self) -> bool {
|
|
self.channel.is_running()
|
|
}
|
|
|
|
/// Stop the DMA transfer and await until the buffer is empty.
|
|
///
|
|
/// This disables the DMA transfer's circular mode so that the transfer
|
|
/// stops when all available data has been written.
|
|
///
|
|
/// This is designed to be used with streaming output data such as the
|
|
/// I2S/SAI or DAC.
|
|
pub async fn stop(&mut self) {
|
|
self.channel.disable_circular_mode();
|
|
//wait until cr.susp reads as true
|
|
poll_fn(|cx| {
|
|
self.set_waker(cx.waker());
|
|
self.channel.poll_stop()
|
|
})
|
|
.await
|
|
}
|
|
}
|
|
|
|
impl<'a, W: Word> Drop for WritableRingBuffer<'a, W> {
|
|
fn drop(&mut self) {
|
|
self.request_stop();
|
|
while self.is_running() {}
|
|
|
|
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
|
fence(Ordering::SeqCst);
|
|
}
|
|
}
|