1050 lines
33 KiB
Rust
1050 lines
33 KiB
Rust
#![macro_use]
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::sync::atomic::{AtomicBool, Ordering};
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use core::task::Poll;
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use embassy_hal_common::into_ref;
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use embassy_sync::waitqueue::AtomicWaker;
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use embassy_usb_driver as driver;
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use embassy_usb_driver::{
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Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
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};
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use super::{DmPin, DpPin, Instance};
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use crate::gpio::sealed::AFType;
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use crate::interrupt::typelevel::Interrupt;
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use crate::pac::usb::regs;
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use crate::pac::usb::vals::{EpType, Stat};
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use crate::pac::USBRAM;
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use crate::rcc::sealed::RccPeripheral;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let regs = T::regs();
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//let x = regs.istr().read().0;
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//trace!("USB IRQ: {:08x}", x);
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let istr = regs.istr().read();
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if istr.susp() {
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//trace!("USB IRQ: susp");
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IRQ_SUSPEND.store(true, Ordering::Relaxed);
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regs.cntr().modify(|w| {
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w.set_fsusp(true);
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w.set_lpmode(true);
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});
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// Write 0 to clear.
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let mut clear = regs::Istr(!0);
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clear.set_susp(false);
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regs.istr().write_value(clear);
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// Wake main thread.
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BUS_WAKER.wake();
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}
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if istr.wkup() {
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//trace!("USB IRQ: wkup");
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IRQ_RESUME.store(true, Ordering::Relaxed);
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regs.cntr().modify(|w| {
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w.set_fsusp(false);
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w.set_lpmode(false);
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});
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// Write 0 to clear.
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let mut clear = regs::Istr(!0);
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clear.set_wkup(false);
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regs.istr().write_value(clear);
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// Wake main thread.
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BUS_WAKER.wake();
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}
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if istr.reset() {
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//trace!("USB IRQ: reset");
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IRQ_RESET.store(true, Ordering::Relaxed);
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// Write 0 to clear.
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let mut clear = regs::Istr(!0);
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clear.set_reset(false);
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regs.istr().write_value(clear);
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// Wake main thread.
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BUS_WAKER.wake();
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}
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if istr.ctr() {
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let index = istr.ep_id() as usize;
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let mut epr = regs.epr(index).read();
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if epr.ctr_rx() {
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if index == 0 && epr.setup() {
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EP0_SETUP.store(true, Ordering::Relaxed);
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}
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//trace!("EP {} RX, setup={}", index, epr.setup());
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EP_OUT_WAKERS[index].wake();
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}
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if epr.ctr_tx() {
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//trace!("EP {} TX", index);
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EP_IN_WAKERS[index].wake();
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}
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epr.set_dtog_rx(false);
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epr.set_dtog_tx(false);
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epr.set_stat_rx(Stat::from_bits(0));
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epr.set_stat_tx(Stat::from_bits(0));
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epr.set_ctr_rx(!epr.ctr_rx());
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epr.set_ctr_tx(!epr.ctr_tx());
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regs.epr(index).write_value(epr);
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}
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}
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}
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const EP_COUNT: usize = 8;
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#[cfg(any(usbram_16x1_512, usbram_16x2_512))]
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const USBRAM_SIZE: usize = 512;
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#[cfg(usbram_16x2_1024)]
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const USBRAM_SIZE: usize = 1024;
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#[cfg(usbram_32_2048)]
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const USBRAM_SIZE: usize = 2048;
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#[cfg(not(usbram_32_2048))]
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const USBRAM_ALIGN: usize = 2;
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#[cfg(usbram_32_2048)]
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const USBRAM_ALIGN: usize = 4;
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const NEW_AW: AtomicWaker = AtomicWaker::new();
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static BUS_WAKER: AtomicWaker = NEW_AW;
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static EP0_SETUP: AtomicBool = AtomicBool::new(false);
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static EP_IN_WAKERS: [AtomicWaker; EP_COUNT] = [NEW_AW; EP_COUNT];
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static EP_OUT_WAKERS: [AtomicWaker; EP_COUNT] = [NEW_AW; EP_COUNT];
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static IRQ_RESET: AtomicBool = AtomicBool::new(false);
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static IRQ_SUSPEND: AtomicBool = AtomicBool::new(false);
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static IRQ_RESUME: AtomicBool = AtomicBool::new(false);
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fn convert_type(t: EndpointType) -> EpType {
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match t {
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EndpointType::Bulk => EpType::BULK,
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EndpointType::Control => EpType::CONTROL,
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EndpointType::Interrupt => EpType::INTERRUPT,
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EndpointType::Isochronous => EpType::ISO,
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}
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}
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fn invariant(mut r: regs::Epr) -> regs::Epr {
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r.set_ctr_rx(true); // don't clear
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r.set_ctr_tx(true); // don't clear
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r.set_dtog_rx(false); // don't toggle
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r.set_dtog_tx(false); // don't toggle
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r.set_stat_rx(Stat::from_bits(0));
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r.set_stat_tx(Stat::from_bits(0));
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r
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}
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fn align_len_up(len: u16) -> u16 {
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((len as usize + USBRAM_ALIGN - 1) / USBRAM_ALIGN * USBRAM_ALIGN) as u16
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}
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// Returns (actual_len, len_bits)
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fn calc_out_len(len: u16) -> (u16, u16) {
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match len {
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// NOTE: this could be 2..=62 with 16bit USBRAM, but not with 32bit. Limit it to 60 for simplicity.
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2..=60 => (align_len_up(len), align_len_up(len) / 2 << 10),
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61..=1024 => ((len + 31) / 32 * 32, (((len + 31) / 32 - 1) << 10) | 0x8000),
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_ => panic!("invalid OUT length {}", len),
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}
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}
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#[cfg(not(usbram_32_2048))]
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mod btable {
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use super::*;
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pub(super) fn write_in<T: Instance>(index: usize, addr: u16) {
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USBRAM.mem(index * 4 + 0).write_value(addr);
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}
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pub(super) fn write_in_len<T: Instance>(index: usize, _addr: u16, len: u16) {
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USBRAM.mem(index * 4 + 1).write_value(len);
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}
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pub(super) fn write_out<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
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USBRAM.mem(index * 4 + 2).write_value(addr);
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USBRAM.mem(index * 4 + 3).write_value(max_len_bits);
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}
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pub(super) fn read_out_len<T: Instance>(index: usize) -> u16 {
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USBRAM.mem(index * 4 + 3).read()
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}
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}
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#[cfg(usbram_32_2048)]
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mod btable {
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use super::*;
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pub(super) fn write_in<T: Instance>(_index: usize, _addr: u16) {}
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pub(super) fn write_in_len<T: Instance>(index: usize, addr: u16, len: u16) {
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USBRAM.mem(index * 2).write_value((addr as u32) | ((len as u32) << 16));
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}
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pub(super) fn write_out<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
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USBRAM
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.mem(index * 2 + 1)
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.write_value((addr as u32) | ((max_len_bits as u32) << 16));
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}
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pub(super) fn read_out_len<T: Instance>(index: usize) -> u16 {
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(USBRAM.mem(index * 2 + 1).read() >> 16) as u16
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}
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}
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struct EndpointBuffer<T: Instance> {
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addr: u16,
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len: u16,
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> EndpointBuffer<T> {
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fn read(&mut self, buf: &mut [u8]) {
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assert!(buf.len() <= self.len as usize);
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for i in 0..(buf.len() + USBRAM_ALIGN - 1) / USBRAM_ALIGN {
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let val = USBRAM.mem(self.addr as usize / USBRAM_ALIGN + i).read();
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let n = USBRAM_ALIGN.min(buf.len() - i * USBRAM_ALIGN);
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buf[i * USBRAM_ALIGN..][..n].copy_from_slice(&val.to_le_bytes()[..n]);
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}
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}
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fn write(&mut self, buf: &[u8]) {
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assert!(buf.len() <= self.len as usize);
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for i in 0..(buf.len() + USBRAM_ALIGN - 1) / USBRAM_ALIGN {
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let mut val = [0u8; USBRAM_ALIGN];
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let n = USBRAM_ALIGN.min(buf.len() - i * USBRAM_ALIGN);
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val[..n].copy_from_slice(&buf[i * USBRAM_ALIGN..][..n]);
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#[cfg(not(usbram_32_2048))]
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let val = u16::from_le_bytes(val);
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#[cfg(usbram_32_2048)]
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let val = u32::from_le_bytes(val);
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USBRAM.mem(self.addr as usize / USBRAM_ALIGN + i).write_value(val);
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}
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}
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}
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#[derive(Debug, Clone, Copy)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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struct EndpointData {
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ep_type: EndpointType, // only valid if used_in || used_out
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used_in: bool,
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used_out: bool,
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}
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pub struct Driver<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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alloc: [EndpointData; EP_COUNT],
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ep_mem_free: u16, // first free address in EP mem, in bytes.
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}
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impl<'d, T: Instance> Driver<'d, T> {
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pub fn new(
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_usb: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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dp: impl Peripheral<P = impl DpPin<T>> + 'd,
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dm: impl Peripheral<P = impl DmPin<T>> + 'd,
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) -> Self {
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into_ref!(dp, dm);
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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let regs = T::regs();
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#[cfg(stm32l5)]
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{
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crate::peripherals::PWR::enable();
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crate::pac::PWR.cr2().modify(|w| w.set_usv(true));
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}
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#[cfg(pwr_h5)]
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crate::pac::PWR.usbscr().modify(|w| w.set_usb33sv(true));
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<T as RccPeripheral>::enable();
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<T as RccPeripheral>::reset();
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regs.cntr().write(|w| {
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w.set_pdwn(false);
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w.set_fres(true);
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});
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#[cfg(time)]
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embassy_time::block_for(embassy_time::Duration::from_millis(100));
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#[cfg(not(time))]
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cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.0 / 10);
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#[cfg(not(usb_v4))]
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regs.btable().write(|w| w.set_btable(0));
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dp.set_as_af(dp.af_num(), AFType::OutputPushPull);
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dm.set_as_af(dm.af_num(), AFType::OutputPushPull);
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// Initialize the bus so that it signals that power is available
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BUS_WAKER.wake();
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Self {
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phantom: PhantomData,
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alloc: [EndpointData {
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ep_type: EndpointType::Bulk,
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used_in: false,
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used_out: false,
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}; EP_COUNT],
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ep_mem_free: EP_COUNT as u16 * 8, // for each EP, 4 regs, so 8 bytes
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}
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}
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fn alloc_ep_mem(&mut self, len: u16) -> u16 {
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assert!(len as usize % USBRAM_ALIGN == 0);
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let addr = self.ep_mem_free;
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if addr + len > USBRAM_SIZE as _ {
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panic!("Endpoint memory full");
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}
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self.ep_mem_free += len;
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addr
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}
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fn alloc_endpoint<D: Dir>(
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&mut self,
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ep_type: EndpointType,
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max_packet_size: u16,
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interval_ms: u8,
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) -> Result<Endpoint<'d, T, D>, driver::EndpointAllocError> {
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trace!(
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"allocating type={:?} mps={:?} interval_ms={}, dir={:?}",
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ep_type,
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max_packet_size,
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interval_ms,
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D::dir()
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);
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let index = self.alloc.iter_mut().enumerate().find(|(i, ep)| {
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if *i == 0 && ep_type != EndpointType::Control {
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return false; // reserved for control pipe
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}
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let used = ep.used_out || ep.used_in;
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let used_dir = match D::dir() {
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Direction::Out => ep.used_out,
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Direction::In => ep.used_in,
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};
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!used || (ep.ep_type == ep_type && !used_dir)
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});
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let (index, ep) = match index {
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Some(x) => x,
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None => return Err(EndpointAllocError),
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};
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ep.ep_type = ep_type;
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let buf = match D::dir() {
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Direction::Out => {
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assert!(!ep.used_out);
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ep.used_out = true;
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let (len, len_bits) = calc_out_len(max_packet_size);
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let addr = self.alloc_ep_mem(len);
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trace!(" len_bits = {:04x}", len_bits);
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btable::write_out::<T>(index, addr, len_bits);
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EndpointBuffer {
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addr,
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len,
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_phantom: PhantomData,
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}
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}
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Direction::In => {
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assert!(!ep.used_in);
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ep.used_in = true;
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let len = align_len_up(max_packet_size);
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let addr = self.alloc_ep_mem(len);
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// ep_in_len is written when actually TXing packets.
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btable::write_in::<T>(index, addr);
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EndpointBuffer {
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addr,
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len,
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_phantom: PhantomData,
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}
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}
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};
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trace!(" index={} addr={} len={}", index, buf.addr, buf.len);
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Ok(Endpoint {
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_phantom: PhantomData,
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info: EndpointInfo {
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addr: EndpointAddress::from_parts(index, D::dir()),
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ep_type,
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max_packet_size,
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interval_ms,
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},
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buf,
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})
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}
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}
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impl<'d, T: Instance> driver::Driver<'d> for Driver<'d, T> {
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type EndpointOut = Endpoint<'d, T, Out>;
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type EndpointIn = Endpoint<'d, T, In>;
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type ControlPipe = ControlPipe<'d, T>;
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type Bus = Bus<'d, T>;
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fn alloc_endpoint_in(
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&mut self,
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ep_type: EndpointType,
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max_packet_size: u16,
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interval_ms: u8,
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) -> Result<Self::EndpointIn, driver::EndpointAllocError> {
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self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
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}
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fn alloc_endpoint_out(
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&mut self,
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ep_type: EndpointType,
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max_packet_size: u16,
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interval_ms: u8,
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) -> Result<Self::EndpointOut, driver::EndpointAllocError> {
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self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
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}
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fn start(mut self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
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let ep_out = self
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.alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
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.unwrap();
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let ep_in = self
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.alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
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.unwrap();
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assert_eq!(ep_out.info.addr.index(), 0);
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assert_eq!(ep_in.info.addr.index(), 0);
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let regs = T::regs();
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regs.cntr().write(|w| {
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w.set_pdwn(false);
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w.set_fres(false);
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w.set_resetm(true);
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w.set_suspm(true);
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w.set_wkupm(true);
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w.set_ctrm(true);
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});
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#[cfg(any(usb_v3, usb_v4))]
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regs.bcdr().write(|w| w.set_dppu(true));
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trace!("enabled");
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let mut ep_types = [EpType::BULK; EP_COUNT - 1];
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for i in 1..EP_COUNT {
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ep_types[i - 1] = convert_type(self.alloc[i].ep_type);
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}
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(
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Bus {
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phantom: PhantomData,
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ep_types,
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inited: false,
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},
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ControlPipe {
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_phantom: PhantomData,
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max_packet_size: control_max_packet_size,
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ep_out,
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ep_in,
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},
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)
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}
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}
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pub struct Bus<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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ep_types: [EpType; EP_COUNT - 1],
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inited: bool,
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}
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impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
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async fn poll(&mut self) -> Event {
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poll_fn(move |cx| {
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BUS_WAKER.register(cx.waker());
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// TODO: implement VBUS detection.
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if !self.inited {
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self.inited = true;
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return Poll::Ready(Event::PowerDetected);
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}
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let regs = T::regs();
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|
|
if IRQ_RESUME.load(Ordering::Acquire) {
|
|
IRQ_RESUME.store(false, Ordering::Relaxed);
|
|
return Poll::Ready(Event::Resume);
|
|
}
|
|
|
|
if IRQ_RESET.load(Ordering::Acquire) {
|
|
IRQ_RESET.store(false, Ordering::Relaxed);
|
|
|
|
trace!("RESET");
|
|
regs.daddr().write(|w| {
|
|
w.set_ef(true);
|
|
w.set_add(0);
|
|
});
|
|
|
|
regs.epr(0).write(|w| {
|
|
w.set_ep_type(EpType::CONTROL);
|
|
w.set_stat_rx(Stat::NAK);
|
|
w.set_stat_tx(Stat::NAK);
|
|
});
|
|
|
|
for i in 1..EP_COUNT {
|
|
regs.epr(i).write(|w| {
|
|
w.set_ea(i as _);
|
|
w.set_ep_type(self.ep_types[i - 1]);
|
|
})
|
|
}
|
|
|
|
for w in &EP_IN_WAKERS {
|
|
w.wake()
|
|
}
|
|
for w in &EP_OUT_WAKERS {
|
|
w.wake()
|
|
}
|
|
|
|
return Poll::Ready(Event::Reset);
|
|
}
|
|
|
|
if IRQ_SUSPEND.load(Ordering::Acquire) {
|
|
IRQ_SUSPEND.store(false, Ordering::Relaxed);
|
|
return Poll::Ready(Event::Suspend);
|
|
}
|
|
|
|
Poll::Pending
|
|
})
|
|
.await
|
|
}
|
|
|
|
fn endpoint_set_stalled(&mut self, ep_addr: EndpointAddress, stalled: bool) {
|
|
// This can race, so do a retry loop.
|
|
let reg = T::regs().epr(ep_addr.index() as _);
|
|
match ep_addr.direction() {
|
|
Direction::In => {
|
|
loop {
|
|
let r = reg.read();
|
|
match r.stat_tx() {
|
|
Stat::DISABLED => break, // if disabled, stall does nothing.
|
|
Stat::STALL => break, // done!
|
|
_ => {
|
|
let want_stat = match stalled {
|
|
false => Stat::NAK,
|
|
true => Stat::STALL,
|
|
};
|
|
let mut w = invariant(r);
|
|
w.set_stat_tx(Stat::from_bits(r.stat_tx().to_bits() ^ want_stat.to_bits()));
|
|
reg.write_value(w);
|
|
}
|
|
}
|
|
}
|
|
EP_IN_WAKERS[ep_addr.index()].wake();
|
|
}
|
|
Direction::Out => {
|
|
loop {
|
|
let r = reg.read();
|
|
match r.stat_rx() {
|
|
Stat::DISABLED => break, // if disabled, stall does nothing.
|
|
Stat::STALL => break, // done!
|
|
_ => {
|
|
let want_stat = match stalled {
|
|
false => Stat::VALID,
|
|
true => Stat::STALL,
|
|
};
|
|
let mut w = invariant(r);
|
|
w.set_stat_rx(Stat::from_bits(r.stat_rx().to_bits() ^ want_stat.to_bits()));
|
|
reg.write_value(w);
|
|
}
|
|
}
|
|
}
|
|
EP_OUT_WAKERS[ep_addr.index()].wake();
|
|
}
|
|
}
|
|
}
|
|
|
|
fn endpoint_is_stalled(&mut self, ep_addr: EndpointAddress) -> bool {
|
|
let regs = T::regs();
|
|
let epr = regs.epr(ep_addr.index() as _).read();
|
|
match ep_addr.direction() {
|
|
Direction::In => epr.stat_tx() == Stat::STALL,
|
|
Direction::Out => epr.stat_rx() == Stat::STALL,
|
|
}
|
|
}
|
|
|
|
fn endpoint_set_enabled(&mut self, ep_addr: EndpointAddress, enabled: bool) {
|
|
trace!("set_enabled {:x} {}", ep_addr, enabled);
|
|
// This can race, so do a retry loop.
|
|
let reg = T::regs().epr(ep_addr.index() as _);
|
|
trace!("EPR before: {:04x}", reg.read().0);
|
|
match ep_addr.direction() {
|
|
Direction::In => {
|
|
loop {
|
|
let want_stat = match enabled {
|
|
false => Stat::DISABLED,
|
|
true => Stat::NAK,
|
|
};
|
|
let r = reg.read();
|
|
if r.stat_tx() == want_stat {
|
|
break;
|
|
}
|
|
let mut w = invariant(r);
|
|
w.set_stat_tx(Stat::from_bits(r.stat_tx().to_bits() ^ want_stat.to_bits()));
|
|
reg.write_value(w);
|
|
}
|
|
EP_IN_WAKERS[ep_addr.index()].wake();
|
|
}
|
|
Direction::Out => {
|
|
loop {
|
|
let want_stat = match enabled {
|
|
false => Stat::DISABLED,
|
|
true => Stat::VALID,
|
|
};
|
|
let r = reg.read();
|
|
if r.stat_rx() == want_stat {
|
|
break;
|
|
}
|
|
let mut w = invariant(r);
|
|
w.set_stat_rx(Stat::from_bits(r.stat_rx().to_bits() ^ want_stat.to_bits()));
|
|
reg.write_value(w);
|
|
}
|
|
EP_OUT_WAKERS[ep_addr.index()].wake();
|
|
}
|
|
}
|
|
trace!("EPR after: {:04x}", reg.read().0);
|
|
}
|
|
|
|
async fn enable(&mut self) {}
|
|
async fn disable(&mut self) {}
|
|
|
|
async fn remote_wakeup(&mut self) -> Result<(), Unsupported> {
|
|
Err(Unsupported)
|
|
}
|
|
}
|
|
|
|
trait Dir {
|
|
fn dir() -> Direction;
|
|
fn waker(i: usize) -> &'static AtomicWaker;
|
|
}
|
|
|
|
pub enum In {}
|
|
impl Dir for In {
|
|
fn dir() -> Direction {
|
|
Direction::In
|
|
}
|
|
|
|
#[inline]
|
|
fn waker(i: usize) -> &'static AtomicWaker {
|
|
&EP_IN_WAKERS[i]
|
|
}
|
|
}
|
|
|
|
pub enum Out {}
|
|
impl Dir for Out {
|
|
fn dir() -> Direction {
|
|
Direction::Out
|
|
}
|
|
|
|
#[inline]
|
|
fn waker(i: usize) -> &'static AtomicWaker {
|
|
&EP_OUT_WAKERS[i]
|
|
}
|
|
}
|
|
|
|
pub struct Endpoint<'d, T: Instance, D> {
|
|
_phantom: PhantomData<(&'d mut T, D)>,
|
|
info: EndpointInfo,
|
|
buf: EndpointBuffer<T>,
|
|
}
|
|
|
|
impl<'d, T: Instance, D> Endpoint<'d, T, D> {
|
|
fn write_data(&mut self, buf: &[u8]) {
|
|
let index = self.info.addr.index();
|
|
self.buf.write(buf);
|
|
btable::write_in_len::<T>(index, self.buf.addr, buf.len() as _);
|
|
}
|
|
|
|
fn read_data(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
|
|
let index = self.info.addr.index();
|
|
let rx_len = btable::read_out_len::<T>(index) as usize & 0x3FF;
|
|
trace!("READ DONE, rx_len = {}", rx_len);
|
|
if rx_len > buf.len() {
|
|
return Err(EndpointError::BufferOverflow);
|
|
}
|
|
self.buf.read(&mut buf[..rx_len]);
|
|
Ok(rx_len)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, In> {
|
|
fn info(&self) -> &EndpointInfo {
|
|
&self.info
|
|
}
|
|
|
|
async fn wait_enabled(&mut self) {
|
|
trace!("wait_enabled OUT WAITING");
|
|
let index = self.info.addr.index();
|
|
poll_fn(|cx| {
|
|
EP_OUT_WAKERS[index].register(cx.waker());
|
|
let regs = T::regs();
|
|
if regs.epr(index).read().stat_tx() == Stat::DISABLED {
|
|
Poll::Pending
|
|
} else {
|
|
Poll::Ready(())
|
|
}
|
|
})
|
|
.await;
|
|
trace!("wait_enabled OUT OK");
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, Out> {
|
|
fn info(&self) -> &EndpointInfo {
|
|
&self.info
|
|
}
|
|
|
|
async fn wait_enabled(&mut self) {
|
|
trace!("wait_enabled OUT WAITING");
|
|
let index = self.info.addr.index();
|
|
poll_fn(|cx| {
|
|
EP_OUT_WAKERS[index].register(cx.waker());
|
|
let regs = T::regs();
|
|
if regs.epr(index).read().stat_rx() == Stat::DISABLED {
|
|
Poll::Pending
|
|
} else {
|
|
Poll::Ready(())
|
|
}
|
|
})
|
|
.await;
|
|
trace!("wait_enabled OUT OK");
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
|
|
trace!("READ WAITING, buf.len() = {}", buf.len());
|
|
let index = self.info.addr.index();
|
|
let stat = poll_fn(|cx| {
|
|
EP_OUT_WAKERS[index].register(cx.waker());
|
|
let regs = T::regs();
|
|
let stat = regs.epr(index).read().stat_rx();
|
|
if matches!(stat, Stat::NAK | Stat::DISABLED) {
|
|
Poll::Ready(stat)
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
if stat == Stat::DISABLED {
|
|
return Err(EndpointError::Disabled);
|
|
}
|
|
|
|
let rx_len = self.read_data(buf)?;
|
|
|
|
let regs = T::regs();
|
|
regs.epr(index).write(|w| {
|
|
w.set_ep_type(convert_type(self.info.ep_type));
|
|
w.set_ea(self.info.addr.index() as _);
|
|
w.set_stat_rx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
|
|
w.set_stat_tx(Stat::from_bits(0));
|
|
w.set_ctr_rx(true); // don't clear
|
|
w.set_ctr_tx(true); // don't clear
|
|
});
|
|
trace!("READ OK, rx_len = {}", rx_len);
|
|
|
|
Ok(rx_len)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
|
|
async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> {
|
|
if buf.len() > self.info.max_packet_size as usize {
|
|
return Err(EndpointError::BufferOverflow);
|
|
}
|
|
|
|
let index = self.info.addr.index();
|
|
|
|
trace!("WRITE WAITING");
|
|
let stat = poll_fn(|cx| {
|
|
EP_IN_WAKERS[index].register(cx.waker());
|
|
let regs = T::regs();
|
|
let stat = regs.epr(index).read().stat_tx();
|
|
if matches!(stat, Stat::NAK | Stat::DISABLED) {
|
|
Poll::Ready(stat)
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
if stat == Stat::DISABLED {
|
|
return Err(EndpointError::Disabled);
|
|
}
|
|
|
|
self.write_data(buf);
|
|
|
|
let regs = T::regs();
|
|
regs.epr(index).write(|w| {
|
|
w.set_ep_type(convert_type(self.info.ep_type));
|
|
w.set_ea(self.info.addr.index() as _);
|
|
w.set_stat_tx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
|
|
w.set_stat_rx(Stat::from_bits(0));
|
|
w.set_ctr_rx(true); // don't clear
|
|
w.set_ctr_tx(true); // don't clear
|
|
});
|
|
|
|
trace!("WRITE OK");
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
pub struct ControlPipe<'d, T: Instance> {
|
|
_phantom: PhantomData<&'d mut T>,
|
|
max_packet_size: u16,
|
|
ep_in: Endpoint<'d, T, In>,
|
|
ep_out: Endpoint<'d, T, Out>,
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
|
|
fn max_packet_size(&self) -> usize {
|
|
usize::from(self.max_packet_size)
|
|
}
|
|
|
|
async fn setup(&mut self) -> [u8; 8] {
|
|
loop {
|
|
trace!("SETUP read waiting");
|
|
poll_fn(|cx| {
|
|
EP_OUT_WAKERS[0].register(cx.waker());
|
|
if EP0_SETUP.load(Ordering::Relaxed) {
|
|
Poll::Ready(())
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
let mut buf = [0; 8];
|
|
let rx_len = self.ep_out.read_data(&mut buf);
|
|
if rx_len != Ok(8) {
|
|
trace!("SETUP read failed: {:?}", rx_len);
|
|
continue;
|
|
}
|
|
|
|
EP0_SETUP.store(false, Ordering::Relaxed);
|
|
|
|
trace!("SETUP read ok");
|
|
return buf;
|
|
}
|
|
}
|
|
|
|
async fn data_out(&mut self, buf: &mut [u8], first: bool, last: bool) -> Result<usize, EndpointError> {
|
|
let regs = T::regs();
|
|
|
|
// When a SETUP is received, Stat/Stat is set to NAK.
|
|
// On first transfer, we must set Stat=VALID, to get the OUT data stage.
|
|
// We want Stat=STALL so that the host gets a STALL if it switches to the status
|
|
// stage too soon, except in the last transfer we set Stat=NAK so that it waits
|
|
// for the status stage, which we will ACK or STALL later.
|
|
if first || last {
|
|
let mut stat_rx = 0;
|
|
let mut stat_tx = 0;
|
|
if first {
|
|
// change NAK -> VALID
|
|
stat_rx ^= Stat::NAK.to_bits() ^ Stat::VALID.to_bits();
|
|
stat_tx ^= Stat::NAK.to_bits() ^ Stat::STALL.to_bits();
|
|
}
|
|
if last {
|
|
// change STALL -> VALID
|
|
stat_tx ^= Stat::STALL.to_bits() ^ Stat::NAK.to_bits();
|
|
}
|
|
// Note: if this is the first AND last transfer, the above effectively
|
|
// changes stat_tx like NAK -> NAK, so noop.
|
|
regs.epr(0).write(|w| {
|
|
w.set_ep_type(EpType::CONTROL);
|
|
w.set_stat_rx(Stat::from_bits(stat_rx));
|
|
w.set_stat_tx(Stat::from_bits(stat_tx));
|
|
w.set_ctr_rx(true); // don't clear
|
|
w.set_ctr_tx(true); // don't clear
|
|
});
|
|
}
|
|
|
|
trace!("data_out WAITING, buf.len() = {}", buf.len());
|
|
poll_fn(|cx| {
|
|
EP_OUT_WAKERS[0].register(cx.waker());
|
|
let regs = T::regs();
|
|
if regs.epr(0).read().stat_rx() == Stat::NAK {
|
|
Poll::Ready(())
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
if EP0_SETUP.load(Ordering::Relaxed) {
|
|
trace!("received another SETUP, aborting data_out.");
|
|
return Err(EndpointError::Disabled);
|
|
}
|
|
|
|
let rx_len = self.ep_out.read_data(buf)?;
|
|
|
|
regs.epr(0).write(|w| {
|
|
w.set_ep_type(EpType::CONTROL);
|
|
w.set_stat_rx(Stat::from_bits(match last {
|
|
// If last, set STAT_RX=STALL.
|
|
true => Stat::NAK.to_bits() ^ Stat::STALL.to_bits(),
|
|
// Otherwise, set STAT_RX=VALID, to allow the host to send the next packet.
|
|
false => Stat::NAK.to_bits() ^ Stat::VALID.to_bits(),
|
|
}));
|
|
w.set_ctr_rx(true); // don't clear
|
|
w.set_ctr_tx(true); // don't clear
|
|
});
|
|
|
|
Ok(rx_len)
|
|
}
|
|
|
|
async fn data_in(&mut self, data: &[u8], first: bool, last: bool) -> Result<(), EndpointError> {
|
|
trace!("control: data_in");
|
|
|
|
if data.len() > self.ep_in.info.max_packet_size as usize {
|
|
return Err(EndpointError::BufferOverflow);
|
|
}
|
|
|
|
let regs = T::regs();
|
|
|
|
// When a SETUP is received, Stat is set to NAK.
|
|
// We want it to be STALL in non-last transfers.
|
|
// We want it to be VALID in last transfer, so the HW does the status stage.
|
|
if first || last {
|
|
let mut stat_rx = 0;
|
|
if first {
|
|
// change NAK -> STALL
|
|
stat_rx ^= Stat::NAK.to_bits() ^ Stat::STALL.to_bits();
|
|
}
|
|
if last {
|
|
// change STALL -> VALID
|
|
stat_rx ^= Stat::STALL.to_bits() ^ Stat::VALID.to_bits();
|
|
}
|
|
// Note: if this is the first AND last transfer, the above effectively
|
|
// does a change of NAK -> VALID.
|
|
regs.epr(0).write(|w| {
|
|
w.set_ep_type(EpType::CONTROL);
|
|
w.set_stat_rx(Stat::from_bits(stat_rx));
|
|
w.set_ep_kind(last); // set OUT_STATUS if last.
|
|
w.set_ctr_rx(true); // don't clear
|
|
w.set_ctr_tx(true); // don't clear
|
|
});
|
|
}
|
|
|
|
trace!("WRITE WAITING");
|
|
poll_fn(|cx| {
|
|
EP_IN_WAKERS[0].register(cx.waker());
|
|
EP_OUT_WAKERS[0].register(cx.waker());
|
|
let regs = T::regs();
|
|
if regs.epr(0).read().stat_tx() == Stat::NAK {
|
|
Poll::Ready(())
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
if EP0_SETUP.load(Ordering::Relaxed) {
|
|
trace!("received another SETUP, aborting data_in.");
|
|
return Err(EndpointError::Disabled);
|
|
}
|
|
|
|
self.ep_in.write_data(data);
|
|
|
|
let regs = T::regs();
|
|
regs.epr(0).write(|w| {
|
|
w.set_ep_type(EpType::CONTROL);
|
|
w.set_stat_tx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
|
|
w.set_ep_kind(last); // set OUT_STATUS if last.
|
|
w.set_ctr_rx(true); // don't clear
|
|
w.set_ctr_tx(true); // don't clear
|
|
});
|
|
|
|
trace!("WRITE OK");
|
|
|
|
Ok(())
|
|
}
|
|
|
|
async fn accept(&mut self) {
|
|
let regs = T::regs();
|
|
trace!("control: accept");
|
|
|
|
self.ep_in.write_data(&[]);
|
|
|
|
// Set OUT=stall, IN=accept
|
|
let epr = regs.epr(0).read();
|
|
regs.epr(0).write(|w| {
|
|
w.set_ep_type(EpType::CONTROL);
|
|
w.set_stat_rx(Stat::from_bits(epr.stat_rx().to_bits() ^ Stat::STALL.to_bits()));
|
|
w.set_stat_tx(Stat::from_bits(epr.stat_tx().to_bits() ^ Stat::VALID.to_bits()));
|
|
w.set_ctr_rx(true); // don't clear
|
|
w.set_ctr_tx(true); // don't clear
|
|
});
|
|
trace!("control: accept WAITING");
|
|
|
|
// Wait is needed, so that we don't set the address too soon, breaking the status stage.
|
|
// (embassy-usb sets the address after accept() returns)
|
|
poll_fn(|cx| {
|
|
EP_IN_WAKERS[0].register(cx.waker());
|
|
let regs = T::regs();
|
|
if regs.epr(0).read().stat_tx() == Stat::NAK {
|
|
Poll::Ready(())
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
trace!("control: accept OK");
|
|
}
|
|
|
|
async fn reject(&mut self) {
|
|
let regs = T::regs();
|
|
trace!("control: reject");
|
|
|
|
// Set IN+OUT to stall
|
|
let epr = regs.epr(0).read();
|
|
regs.epr(0).write(|w| {
|
|
w.set_ep_type(EpType::CONTROL);
|
|
w.set_stat_rx(Stat::from_bits(epr.stat_rx().to_bits() ^ Stat::STALL.to_bits()));
|
|
w.set_stat_tx(Stat::from_bits(epr.stat_tx().to_bits() ^ Stat::STALL.to_bits()));
|
|
w.set_ctr_rx(true); // don't clear
|
|
w.set_ctr_tx(true); // don't clear
|
|
});
|
|
}
|
|
|
|
async fn accept_set_address(&mut self, addr: u8) {
|
|
self.accept().await;
|
|
|
|
let regs = T::regs();
|
|
trace!("setting addr: {}", addr);
|
|
regs.daddr().write(|w| {
|
|
w.set_ef(true);
|
|
w.set_add(addr);
|
|
});
|
|
}
|
|
}
|