2b7e76efe9
This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup. Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration. This ensures that each core will only handle the interrupts of the DMA channels that it uses.
504 lines
16 KiB
Rust
504 lines
16 KiB
Rust
use stm32_metapac::flash::vals::Latency;
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
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Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
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};
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#[cfg(any(stm32f4, stm32f7))]
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use crate::pac::PWR;
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use crate::pac::{FLASH, RCC};
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use crate::time::Hertz;
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// TODO: on some F4s, PLLM is shared between all PLLs. Enforce that.
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// TODO: on some F4s, add support for plli2s_src
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//
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// plli2s plli2s_m plli2s_src pllsai pllsai_m
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// f401 y shared
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// f410
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// f411 y individual
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// f412 y individual y
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// f4[12]3 y individual y
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// f446 y individual y individual
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// f4[67]9 y shared y shared
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// f4[23][79] y shared y shared
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// f4[01][57] y shared
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1)
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Bypass,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// PLL pre-divider (DIVM).
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pub prediv: PllPreDiv,
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/// PLL multiplication factor.
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pub mul: PllMul,
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/// PLL P division factor. If None, PLL P output is disabled.
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pub divp: Option<PllPDiv>,
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/// PLL Q division factor. If None, PLL Q output is disabled.
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pub divq: Option<PllQDiv>,
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/// PLL R division factor. If None, PLL R output is disabled.
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pub divr: Option<PllRDiv>,
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}
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/// Voltage range of the power supply used.
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///
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/// Used to calculate flash waitstates. See
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/// RM0033 - Table 3. Number of wait states according to Cortex®-M3 clock frequency
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#[cfg(stm32f2)]
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#[derive(Clone, Copy)]
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pub enum VoltageScale {
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/// 2.7 to 3.6 V
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Range0,
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/// 2.4 to 2.7 V
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Range1,
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/// 2.1 to 2.4 V
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Range2,
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/// 1.8 to 2.1 V
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Range3,
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}
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/// Configuration of the core clocks
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#[non_exhaustive]
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#[derive(Clone, Copy)]
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pub struct Config {
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pub hsi: bool,
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pub hse: Option<Hse>,
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pub sys: Sysclk,
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pub pll_src: PllSource,
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pub pll: Option<Pll>,
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#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
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pub plli2s: Option<Pll>,
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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pub pllsai: Option<Pll>,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub ls: super::LsConfig,
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/// Per-peripheral kernel clock selection muxes
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pub mux: super::mux::ClockMux,
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#[cfg(stm32f2)]
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pub voltage: VoltageScale,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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hsi: true,
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hse: None,
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sys: Sysclk::HSI,
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pll_src: PllSource::HSI,
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pll: None,
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#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
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plli2s: None,
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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pllsai: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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ls: Default::default(),
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#[cfg(stm32f2)]
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voltage: VoltageScale::Range3,
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mux: Default::default(),
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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// set VOS to SCALE1, if use PLL
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// TODO: check real clock speed before set VOS
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#[cfg(any(stm32f4, stm32f7))]
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if config.pll.is_some() {
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PWR.cr1().modify(|w| w.set_vos(crate::pac::pwr::vals::Vos::SCALE1));
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}
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// always enable overdrive for now. Make it configurable in the future.
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#[cfg(any(stm32f446, stm32f4x9, stm32f427, stm32f437, stm32f7))]
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{
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PWR.cr1().modify(|w| w.set_oden(true));
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while !PWR.csr1().read().odrdy() {}
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PWR.cr1().modify(|w| w.set_odswen(true));
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while !PWR.csr1().read().odswrdy() {}
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}
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// Turn on the HSI
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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// Use the HSI clock as system clock during the actual clock setup
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RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
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while RCC.cfgr().read().sws() != Sysclk::HSI {}
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// Configure HSI
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let hsi = match config.hsi {
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false => None,
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true => Some(HSI_FREQ),
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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match hse.mode {
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HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
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HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
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}
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RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// Configure PLLs.
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let pll_input = PllInput {
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hse,
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hsi,
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source: config.pll_src,
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};
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let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
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#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
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let plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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let pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
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// Configure sysclk
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let sys = match config.sys {
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Sysclk::HSI => unwrap!(hsi),
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Sysclk::HSE => unwrap!(hse),
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Sysclk::PLL1_P => unwrap!(pll.p),
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_ => unreachable!(),
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};
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let hclk = sys / config.ahb_pre;
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
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let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
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assert!(max::SYSCLK.contains(&sys));
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assert!(max::HCLK.contains(&hclk));
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assert!(max::PCLK1.contains(&pclk1));
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assert!(max::PCLK2.contains(&pclk2));
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let rtc = config.ls.init();
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#[cfg(stm32f2)]
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let latency = match (config.voltage, hclk.0) {
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(VoltageScale::Range3, ..=16_000_000) => Latency::WS0,
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(VoltageScale::Range3, ..=32_000_000) => Latency::WS1,
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(VoltageScale::Range3, ..=48_000_000) => Latency::WS2,
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(VoltageScale::Range3, ..=64_000_000) => Latency::WS3,
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(VoltageScale::Range3, ..=80_000_000) => Latency::WS4,
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(VoltageScale::Range3, ..=96_000_000) => Latency::WS5,
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(VoltageScale::Range3, ..=112_000_000) => Latency::WS6,
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(VoltageScale::Range3, ..=120_000_000) => Latency::WS7,
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(VoltageScale::Range2, ..=18_000_000) => Latency::WS0,
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(VoltageScale::Range2, ..=36_000_000) => Latency::WS1,
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(VoltageScale::Range2, ..=54_000_000) => Latency::WS2,
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(VoltageScale::Range2, ..=72_000_000) => Latency::WS3,
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(VoltageScale::Range2, ..=90_000_000) => Latency::WS4,
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(VoltageScale::Range2, ..=108_000_000) => Latency::WS5,
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(VoltageScale::Range2, ..=120_000_000) => Latency::WS6,
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(VoltageScale::Range1, ..=24_000_000) => Latency::WS0,
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(VoltageScale::Range1, ..=48_000_000) => Latency::WS1,
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(VoltageScale::Range1, ..=72_000_000) => Latency::WS2,
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(VoltageScale::Range1, ..=96_000_000) => Latency::WS3,
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(VoltageScale::Range1, ..=120_000_000) => Latency::WS4,
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(VoltageScale::Range0, ..=30_000_000) => Latency::WS0,
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(VoltageScale::Range0, ..=60_000_000) => Latency::WS1,
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(VoltageScale::Range0, ..=90_000_000) => Latency::WS2,
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(VoltageScale::Range0, ..=120_000_000) => Latency::WS3,
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_ => unreachable!(),
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};
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#[cfg(any(stm32f4, stm32f7))]
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let latency = {
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// Be conservative with voltage ranges
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const FLASH_LATENCY_STEP: u32 = 30_000_000;
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let latency = (hclk.0 - 1) / FLASH_LATENCY_STEP;
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debug!("flash: latency={}", latency);
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Latency::from_bits(latency as u8)
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};
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FLASH.acr().write(|w| w.set_latency(latency));
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while FLASH.acr().read().latency() != latency {}
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RCC.cfgr().modify(|w| {
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w.set_sw(config.sys);
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w.set_hpre(config.ahb_pre);
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w.set_ppre1(config.apb1_pre);
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w.set_ppre2(config.apb2_pre);
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});
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while RCC.cfgr().read().sws() != config.sys {}
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// Disable HSI if not used
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if !config.hsi {
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RCC.cr().modify(|w| w.set_hsion(false));
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}
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config.mux.init();
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set_clocks!(
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hsi: hsi,
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hse: hse,
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lse: None, // TODO
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lsi: None, // TODO
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sys: Some(sys),
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hclk1: Some(hclk),
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hclk2: Some(hclk),
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hclk3: Some(hclk),
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pclk1: Some(pclk1),
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pclk2: Some(pclk2),
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pclk1_tim: Some(pclk1_tim),
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pclk2_tim: Some(pclk2_tim),
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rtc: rtc,
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pll1_q: pll.q,
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pll1_r: pll.r,
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#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
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plli2s1_p: plli2s.p,
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#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
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plli2s1_q: plli2s.q,
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#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
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plli2s1_r: plli2s.r,
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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pllsai1_p: pllsai.p,
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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pllsai1_q: pllsai.q,
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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pllsai1_r: pllsai.r,
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// TODO workaround until f4 rcc is fixed in stm32-data
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#[cfg(not(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7)))]
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pllsai1_q: None,
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#[cfg(dsihost)]
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dsi_phy: None, // DSI PLL clock not supported, don't call `RccPeripheral::frequency()` in the drivers
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hsi_div488: hsi.map(|hsi| hsi/488u32),
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hsi_hse: None,
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afif: None,
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);
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}
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struct PllInput {
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source: PllSource,
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hsi: Option<Hertz>,
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hse: Option<Hertz>,
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}
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#[derive(Default)]
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#[allow(unused)]
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struct PllOutput {
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p: Option<Hertz>,
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q: Option<Hertz>,
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r: Option<Hertz>,
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}
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#[derive(PartialEq, Eq, Clone, Copy)]
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enum PllInstance {
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Pll,
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#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
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Plli2s,
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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Pllsai,
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}
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fn pll_enable(instance: PllInstance, enabled: bool) {
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match instance {
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PllInstance::Pll => {
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RCC.cr().modify(|w| w.set_pllon(enabled));
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while RCC.cr().read().pllrdy() != enabled {}
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}
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#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
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PllInstance::Plli2s => {
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RCC.cr().modify(|w| w.set_plli2son(enabled));
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while RCC.cr().read().plli2srdy() != enabled {}
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}
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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PllInstance::Pllsai => {
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RCC.cr().modify(|w| w.set_pllsaion(enabled));
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while RCC.cr().read().pllsairdy() != enabled {}
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}
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}
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}
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fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
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// Disable PLL
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pll_enable(instance, false);
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let Some(pll) = config else { return PllOutput::default() };
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let pll_src = match input.source {
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PllSource::HSE => input.hse,
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PllSource::HSI => input.hsi,
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};
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let pll_src = pll_src.unwrap();
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let in_freq = pll_src / pll.prediv;
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assert!(max::PLL_IN.contains(&in_freq));
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let vco_freq = in_freq * pll.mul;
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assert!(max::PLL_VCO.contains(&vco_freq));
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// stm32f2 plls are like swiss cheese
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#[cfg(stm32f2)]
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match instance {
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PllInstance::Pll => {
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assert!(pll.divr.is_none());
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}
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PllInstance::Plli2s => {
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assert!(pll.divp.is_none());
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assert!(pll.divq.is_none());
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}
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}
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let p = pll.divp.map(|div| vco_freq / div);
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let q = pll.divq.map(|div| vco_freq / div);
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let r = pll.divr.map(|div| vco_freq / div);
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macro_rules! write_fields {
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($w:ident) => {
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$w.set_plln(pll.mul);
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if let Some(divp) = pll.divp {
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$w.set_pllp(divp);
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}
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if let Some(divq) = pll.divq {
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$w.set_pllq(divq);
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}
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#[cfg(any(stm32f4, stm32f7))]
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if let Some(divr) = pll.divr {
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$w.set_pllr(divr);
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}
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};
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}
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match instance {
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PllInstance::Pll => RCC.pllcfgr().write(|w| {
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w.set_pllm(pll.prediv);
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w.set_pllsrc(input.source);
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write_fields!(w);
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}),
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#[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
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PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
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write_fields!(w);
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}),
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#[cfg(stm32f2)]
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PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
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if let Some(divr) = pll.divr {
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w.set_pllr(divr);
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}
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}),
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#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
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PllInstance::Pllsai => RCC.pllsaicfgr().write(|w| {
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write_fields!(w);
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}),
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}
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// Enable PLL
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pll_enable(instance, true);
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PllOutput { p, q, r }
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}
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#[cfg(stm32f7)]
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mod max {
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use core::ops::RangeInclusive;
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use crate::time::Hertz;
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pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
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pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
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pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
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pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
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pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000 / 4);
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pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000 / 2);
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pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
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pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
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}
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#[cfg(stm32f4)]
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mod max {
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use core::ops::RangeInclusive;
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use crate::time::Hertz;
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pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
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pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
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#[cfg(stm32f401)]
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pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(84_000_000);
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#[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
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pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(168_000_000);
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#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
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pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(100_000_000);
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
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pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(180_000_000);
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pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0);
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pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(PCLK2.end().0 / 2);
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#[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
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pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(HCLK.end().0);
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#[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
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pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(HCLK.end().0 / 2);
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pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
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pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
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}
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#[cfg(stm32f2)]
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mod max {
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use core::ops::RangeInclusive;
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use crate::time::Hertz;
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pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
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pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(26_000_000);
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pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(120_000_000);
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pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0);
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pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0 / 4);
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pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0 / 2);
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pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(0_950_000)..=Hertz(2_100_000);
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pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(432_000_000);
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}
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