194 lines
4.6 KiB
Rust
194 lines
4.6 KiB
Rust
//! Interrupt management
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//!
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//! This module implements an API for managing interrupts compatible with
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//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time.
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use core::sync::atomic::{compiler_fence, Ordering};
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use crate::pac::NVIC_PRIO_BITS;
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// Re-exports
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pub use crate::pac::Interrupt;
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pub use crate::pac::Interrupt::*; // needed for cortex-m-rt #[interrupt]
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pub use cortex_m::interrupt::{CriticalSection, Mutex};
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pub use embassy::interrupt::{declare, take, OwnedInterrupt};
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#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[repr(u8)]
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pub enum Priority {
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Level0 = 0,
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Level1 = 1,
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Level2 = 2,
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Level3 = 3,
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Level4 = 4,
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Level5 = 5,
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Level6 = 6,
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Level7 = 7,
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Level8 = 8,
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Level9 = 9,
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Level10 = 10,
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Level11 = 11,
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Level12 = 12,
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Level13 = 13,
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Level14 = 14,
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Level15 = 15,
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}
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impl From<u8> for Priority {
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fn from(priority: u8) -> Self {
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match priority >> (8 - NVIC_PRIO_BITS) {
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0 => Self::Level0,
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1 => Self::Level1,
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2 => Self::Level2,
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3 => Self::Level3,
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4 => Self::Level4,
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5 => Self::Level5,
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6 => Self::Level6,
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7 => Self::Level7,
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8 => Self::Level8,
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9 => Self::Level9,
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10 => Self::Level10,
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11 => Self::Level11,
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12 => Self::Level12,
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13 => Self::Level13,
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14 => Self::Level14,
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15 => Self::Level15,
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_ => unreachable!(),
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}
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}
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}
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impl From<Priority> for u8 {
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fn from(p: Priority) -> Self {
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(p as u8) << (8 - NVIC_PRIO_BITS)
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}
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}
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#[inline]
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pub fn free<F, R>(f: F) -> R
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where
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F: FnOnce(&CriticalSection) -> R,
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{
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unsafe {
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// TODO: assert that we're in privileged level
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// Needed because disabling irqs in non-privileged level is a noop, which would break safety.
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let primask: u32;
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asm!("mrs {}, PRIMASK", out(reg) primask);
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asm!("cpsid i");
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// Prevent compiler from reordering operations inside/outside the critical section.
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compiler_fence(Ordering::SeqCst);
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let r = f(&CriticalSection::new());
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compiler_fence(Ordering::SeqCst);
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if primask & 1 == 0 {
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asm!("cpsie i");
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}
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r
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}
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}
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#[cfg(feature = "stm32f405")]
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mod irqs {
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use super::*;
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declare!(WWDG);
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declare!(PVD);
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declare!(TAMP_STAMP);
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declare!(RTC_WKUP);
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// declare!(FLASH);
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declare!(RCC);
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declare!(EXTI0);
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declare!(EXTI1);
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declare!(EXTI2);
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declare!(EXTI3);
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declare!(EXTI4);
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declare!(DMA1_STREAM0);
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declare!(DMA1_STREAM1);
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declare!(DMA1_STREAM2);
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declare!(DMA1_STREAM3);
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declare!(DMA1_STREAM4);
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declare!(DMA1_STREAM5);
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declare!(DMA1_STREAM6);
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declare!(ADC);
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declare!(CAN1_TX);
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declare!(CAN1_RX0);
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declare!(CAN1_RX1);
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declare!(CAN1_SCE);
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declare!(EXTI9_5);
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declare!(TIM1_BRK_TIM9);
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declare!(TIM1_UP_TIM10);
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declare!(TIM1_TRG_COM_TIM11);
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declare!(TIM1_CC);
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declare!(TIM2);
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declare!(TIM3);
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declare!(TIM4);
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declare!(I2C1_EV);
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declare!(I2C1_ER);
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declare!(I2C2_EV);
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declare!(I2C2_ER);
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declare!(SPI1);
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declare!(SPI2);
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declare!(USART1);
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declare!(USART2);
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declare!(USART3);
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declare!(EXTI15_10);
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declare!(RTC_ALARM);
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declare!(OTG_FS_WKUP);
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declare!(TIM8_BRK_TIM12);
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declare!(TIM8_UP_TIM13);
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declare!(TIM8_TRG_COM_TIM14);
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declare!(TIM8_CC);
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declare!(DMA1_STREAM7);
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// declare!(FMC);
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declare!(SDIO);
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declare!(TIM5);
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declare!(SPI3);
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declare!(UART4);
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declare!(UART5);
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declare!(TIM6_DAC);
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declare!(TIM7);
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declare!(DMA2_STREAM0);
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declare!(DMA2_STREAM1);
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declare!(DMA2_STREAM2);
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declare!(DMA2_STREAM3);
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declare!(DMA2_STREAM4);
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declare!(ETH);
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declare!(ETH_WKUP);
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declare!(CAN2_TX);
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declare!(CAN2_RX0);
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declare!(CAN2_RX1);
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declare!(CAN2_SCE);
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declare!(OTG_FS);
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declare!(DMA2_STREAM5);
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declare!(DMA2_STREAM6);
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declare!(DMA2_STREAM7);
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declare!(USART6);
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declare!(I2C3_EV);
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declare!(I2C3_ER);
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declare!(OTG_HS_EP1_OUT);
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declare!(OTG_HS_EP1_IN);
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declare!(OTG_HS_WKUP);
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declare!(OTG_HS);
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declare!(DCMI);
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declare!(CRYP);
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declare!(HASH_RNG);
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declare!(FPU);
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// declare!(UART7);
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// declare!(UART8);
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// declare!(SPI4);
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// declare!(SPI5);
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// declare!(SPI6);
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// declare!(SAI1);
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declare!(LCD_TFT);
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declare!(LCD_TFT_1);
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// declare!(DMA2D);
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}
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pub use irqs::*;
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