478 lines
18 KiB
Rust
478 lines
18 KiB
Rust
#![no_std]
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#![cfg_attr(
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feature = "nightly",
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feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections)
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)]
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#![cfg_attr(feature = "nightly", allow(incomplete_features))]
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#![doc = include_str!("../README.md")]
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#![warn(missing_docs)]
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#[cfg(not(any(
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feature = "nrf51",
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feature = "nrf52805",
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feature = "nrf52810",
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feature = "nrf52811",
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feature = "nrf52820",
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feature = "nrf52832",
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feature = "nrf52833",
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feature = "nrf52840",
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feature = "nrf5340-app-s",
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feature = "nrf5340-app-ns",
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feature = "nrf5340-net",
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feature = "nrf9160-s",
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feature = "nrf9160-ns",
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)))]
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compile_error!("No chip feature activated. You must activate exactly one of the following features: nrf52810, nrf52811, nrf52832, nrf52833, nrf52840");
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#[cfg(all(feature = "reset-pin-as-gpio", not(feature = "_nrf52")))]
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compile_error!("feature `reset-pin-as-gpio` is only valid for nRF52 series chips.");
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#[cfg(all(feature = "nfc-pins-as-gpio", not(any(feature = "_nrf52", feature = "_nrf5340-app"))))]
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compile_error!("feature `nfc-pins-as-gpio` is only valid for nRF52, or nRF53's application core.");
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// This mod MUST go first, so that the others see its macros.
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pub(crate) mod fmt;
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pub(crate) mod util;
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#[cfg(feature = "_time-driver")]
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mod time_driver;
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pub mod buffered_uarte;
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pub mod gpio;
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#[cfg(feature = "gpiote")]
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pub mod gpiote;
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#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
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pub mod i2s;
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pub mod nvmc;
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#[cfg(any(
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feature = "nrf52810",
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feature = "nrf52811",
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feature = "nrf52832",
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feature = "nrf52833",
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feature = "nrf52840",
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feature = "_nrf5340-app",
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feature = "_nrf9160"
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))]
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pub mod pdm;
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pub mod ppi;
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#[cfg(not(any(feature = "nrf52805", feature = "nrf52820", feature = "_nrf5340-net")))]
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pub mod pwm;
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#[cfg(not(any(feature = "nrf51", feature = "_nrf9160", feature = "_nrf5340-net")))]
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pub mod qdec;
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#[cfg(any(feature = "nrf52840", feature = "_nrf5340-app"))]
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pub mod qspi;
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#[cfg(not(any(feature = "_nrf5340-app", feature = "_nrf9160")))]
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pub mod rng;
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#[cfg(not(any(feature = "nrf52820", feature = "_nrf5340-net")))]
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pub mod saadc;
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pub mod spim;
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pub mod spis;
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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pub mod temp;
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pub mod timer;
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pub mod twim;
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pub mod twis;
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pub mod uarte;
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#[cfg(any(
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feature = "_nrf5340-app",
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feature = "nrf52820",
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feature = "nrf52833",
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feature = "nrf52840"
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))]
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#[cfg(feature = "nightly")]
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pub mod usb;
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#[cfg(not(feature = "_nrf5340"))]
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pub mod wdt;
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// This mod MUST go last, so that it sees all the `impl_foo!` macros
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#[cfg_attr(feature = "nrf52805", path = "chips/nrf52805.rs")]
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#[cfg_attr(feature = "nrf52810", path = "chips/nrf52810.rs")]
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#[cfg_attr(feature = "nrf52811", path = "chips/nrf52811.rs")]
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#[cfg_attr(feature = "nrf52820", path = "chips/nrf52820.rs")]
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#[cfg_attr(feature = "nrf52832", path = "chips/nrf52832.rs")]
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#[cfg_attr(feature = "nrf52833", path = "chips/nrf52833.rs")]
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#[cfg_attr(feature = "nrf52840", path = "chips/nrf52840.rs")]
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#[cfg_attr(feature = "_nrf5340-app", path = "chips/nrf5340_app.rs")]
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#[cfg_attr(feature = "_nrf5340-net", path = "chips/nrf5340_net.rs")]
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#[cfg_attr(feature = "_nrf9160", path = "chips/nrf9160.rs")]
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mod chip;
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pub mod interrupt {
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//! Interrupt definitions and macros to bind them.
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pub use cortex_m::interrupt::{CriticalSection, Mutex};
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pub use embassy_cortex_m::interrupt::*;
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pub use crate::chip::irqs::*;
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/// Macro to bind interrupts to handlers.
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///
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/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
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/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
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/// prove at compile-time that the right interrupts have been bound.
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// developer note: this macro can't be in `embassy-cortex-m` due to the use of `$crate`.
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#[macro_export]
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macro_rules! bind_interrupts {
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($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
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$vis struct $name;
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$(
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#[allow(non_snake_case)]
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#[no_mangle]
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unsafe extern "C" fn $irq() {
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$(
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<$handler as $crate::interrupt::Handler<$crate::interrupt::$irq>>::on_interrupt();
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)*
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}
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$(
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unsafe impl $crate::interrupt::Binding<$crate::interrupt::$irq, $handler> for $name {}
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)*
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)*
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};
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}
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}
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// Reexports
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#[cfg(feature = "unstable-pac")]
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pub use chip::pac;
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#[cfg(not(feature = "unstable-pac"))]
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pub(crate) use chip::pac;
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pub use chip::{peripherals, Peripherals, EASY_DMA_SIZE};
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pub use embassy_cortex_m::executor;
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pub use embassy_cortex_m::interrupt::_export::interrupt;
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pub use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
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pub mod config {
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//! Configuration options used when initializing the HAL.
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/// High frequency clock source.
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pub enum HfclkSource {
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/// Internal source
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Internal,
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/// External source from xtal.
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ExternalXtal,
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}
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/// Low frequency clock source
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pub enum LfclkSource {
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/// Internal RC oscillator
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InternalRC,
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/// Synthesized from the high frequency clock source.
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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Synthesized,
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/// External source from xtal.
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ExternalXtal,
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/// External source from xtal with low swing applied.
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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ExternalLowSwing,
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/// External source from xtal with full swing applied.
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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ExternalFullSwing,
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}
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/// SWD access port protection setting.
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#[non_exhaustive]
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pub enum Debug {
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/// Debugging is allowed (APPROTECT is disabled). Default.
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Allowed,
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/// Debugging is not allowed (APPROTECT is enabled).
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Disallowed,
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/// APPROTECT is not configured (neither to enable it or disable it).
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/// This can be useful if you're already doing it by other means and
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/// you don't want embassy-nrf to touch UICR.
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NotConfigured,
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}
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/// Configuration for peripherals. Default configuration should work on any nRF chip.
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#[non_exhaustive]
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pub struct Config {
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/// High frequency clock source.
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pub hfclk_source: HfclkSource,
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/// Low frequency clock source.
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pub lfclk_source: LfclkSource,
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/// GPIOTE interrupt priority. Should be lower priority than softdevice if used.
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#[cfg(feature = "gpiote")]
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pub gpiote_interrupt_priority: crate::interrupt::Priority,
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/// Time driver interrupt priority. Should be lower priority than softdevice if used.
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#[cfg(feature = "_time-driver")]
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pub time_interrupt_priority: crate::interrupt::Priority,
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/// Enable or disable the debug port.
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pub debug: Debug,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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// There are hobby nrf52 boards out there without external XTALs...
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// Default everything to internal so it Just Works. User can enable external
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// xtals if they know they have them.
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hfclk_source: HfclkSource::Internal,
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lfclk_source: LfclkSource::InternalRC,
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#[cfg(feature = "gpiote")]
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gpiote_interrupt_priority: crate::interrupt::Priority::P0,
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#[cfg(feature = "_time-driver")]
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time_interrupt_priority: crate::interrupt::Priority::P0,
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// In NS mode, default to NotConfigured, assuming the S firmware will do it.
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#[cfg(feature = "_ns")]
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debug: Debug::NotConfigured,
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#[cfg(not(feature = "_ns"))]
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debug: Debug::Allowed,
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}
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}
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}
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}
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#[cfg(feature = "_nrf9160")]
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#[allow(unused)]
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mod consts {
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pub const UICR_APPROTECT: *mut u32 = 0x00FF8000 as *mut u32;
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pub const UICR_SECUREAPPROTECT: *mut u32 = 0x00FF802C as *mut u32;
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pub const APPROTECT_ENABLED: u32 = 0x0000_0000;
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}
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#[cfg(feature = "_nrf5340-app")]
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#[allow(unused)]
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mod consts {
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pub const UICR_APPROTECT: *mut u32 = 0x00FF8000 as *mut u32;
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pub const UICR_SECUREAPPROTECT: *mut u32 = 0x00FF801C as *mut u32;
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pub const UICR_NFCPINS: *mut u32 = 0x00FF8028 as *mut u32;
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pub const APPROTECT_ENABLED: u32 = 0x0000_0000;
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pub const APPROTECT_DISABLED: u32 = 0x50FA50FA;
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}
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#[cfg(feature = "_nrf5340-net")]
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#[allow(unused)]
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mod consts {
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pub const UICR_APPROTECT: *mut u32 = 0x01FF8000 as *mut u32;
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pub const APPROTECT_ENABLED: u32 = 0x0000_0000;
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pub const APPROTECT_DISABLED: u32 = 0x50FA50FA;
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}
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#[cfg(feature = "_nrf52")]
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#[allow(unused)]
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mod consts {
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pub const UICR_PSELRESET1: *mut u32 = 0x10001200 as *mut u32;
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pub const UICR_PSELRESET2: *mut u32 = 0x10001204 as *mut u32;
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pub const UICR_NFCPINS: *mut u32 = 0x1000120C as *mut u32;
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pub const UICR_APPROTECT: *mut u32 = 0x10001208 as *mut u32;
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pub const APPROTECT_ENABLED: u32 = 0x0000_0000;
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pub const APPROTECT_DISABLED: u32 = 0x0000_005a;
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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enum WriteResult {
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/// Word was written successfully, needs reset.
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Written,
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/// Word was already set to the value we wanted to write, nothing was done.
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Noop,
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/// Word is already set to something else, we couldn't write the desired value.
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Failed,
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}
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unsafe fn uicr_write(address: *mut u32, value: u32) -> WriteResult {
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let curr_val = address.read_volatile();
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if curr_val == value {
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return WriteResult::Noop;
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}
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// We can only change `1` bits to `0` bits.
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if curr_val & value != value {
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return WriteResult::Failed;
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}
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// Writing to UICR can only change `1` bits to `0` bits.
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// If this write would change `0` bits to `1` bits, we can't do it.
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// It is only possible to do when erasing UICR, which is forbidden if
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// APPROTECT is enabled.
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if (!curr_val) & value != 0 {
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panic!("Cannot write UICR address={:08x} value={:08x}", address as u32, value)
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}
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let nvmc = &*pac::NVMC::ptr();
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nvmc.config.write(|w| w.wen().wen());
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while nvmc.ready.read().ready().is_busy() {}
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address.write_volatile(value);
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while nvmc.ready.read().ready().is_busy() {}
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nvmc.config.reset();
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while nvmc.ready.read().ready().is_busy() {}
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WriteResult::Written
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}
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/// Initialize peripherals with the provided configuration. This should only be called once at startup.
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pub fn init(config: config::Config) -> Peripherals {
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// Do this first, so that it panics if user is calling `init` a second time
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// before doing anything important.
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let peripherals = Peripherals::take();
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let mut needs_reset = false;
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// Setup debug protection.
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match config.debug {
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config::Debug::Allowed => {
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#[cfg(feature = "_nrf52")]
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unsafe {
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let variant = (0x1000_0104 as *mut u32).read_volatile();
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// Get the letter for the build code (b'A' .. b'F')
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let build_code = (variant >> 8) as u8;
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if build_code >= b'F' {
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// Chips with build code F and higher (revision 3 and higher) have an
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// improved APPROTECT ("hardware and software controlled access port protection")
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// which needs explicit action by the firmware to keep it unlocked
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// UICR.APPROTECT = SwDisabled
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let res = uicr_write(consts::UICR_APPROTECT, consts::APPROTECT_DISABLED);
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needs_reset |= res == WriteResult::Written;
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// APPROTECT.DISABLE = SwDisabled
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(0x4000_0558 as *mut u32).write_volatile(consts::APPROTECT_DISABLED);
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} else {
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// nothing to do on older chips, debug is allowed by default.
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}
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}
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#[cfg(feature = "_nrf5340")]
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unsafe {
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let p = &*pac::CTRLAP::ptr();
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let res = uicr_write(consts::UICR_APPROTECT, consts::APPROTECT_DISABLED);
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needs_reset |= res == WriteResult::Written;
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p.approtect.disable.write(|w| w.bits(consts::APPROTECT_DISABLED));
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#[cfg(feature = "_nrf5340-app")]
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{
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let res = uicr_write(consts::UICR_SECUREAPPROTECT, consts::APPROTECT_DISABLED);
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needs_reset |= res == WriteResult::Written;
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p.secureapprotect.disable.write(|w| w.bits(consts::APPROTECT_DISABLED));
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}
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}
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// nothing to do on the nrf9160, debug is allowed by default.
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}
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config::Debug::Disallowed => unsafe {
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// UICR.APPROTECT = Enabled
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let res = uicr_write(consts::UICR_APPROTECT, consts::APPROTECT_ENABLED);
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needs_reset |= res == WriteResult::Written;
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#[cfg(any(feature = "_nrf5340-app", feature = "_nrf9160"))]
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{
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let res = uicr_write(consts::UICR_SECUREAPPROTECT, consts::APPROTECT_ENABLED);
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needs_reset |= res == WriteResult::Written;
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}
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},
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config::Debug::NotConfigured => {}
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}
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#[cfg(feature = "_nrf52")]
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unsafe {
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let value = if cfg!(feature = "reset-pin-as-gpio") {
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!0
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} else {
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chip::RESET_PIN
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};
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let res1 = uicr_write(consts::UICR_PSELRESET1, value);
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let res2 = uicr_write(consts::UICR_PSELRESET2, value);
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needs_reset |= res1 == WriteResult::Written || res2 == WriteResult::Written;
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if res1 == WriteResult::Failed || res2 == WriteResult::Failed {
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#[cfg(not(feature = "reset-pin-as-gpio"))]
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warn!(
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"You have requested enabling chip reset functionality on the reset pin, by not enabling the Cargo feature `reset-pin-as-gpio`.\n\
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However, UICR is already programmed to some other setting, and can't be changed without erasing it.\n\
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To fix this, erase UICR manually, for example using `probe-rs-cli erase` or `nrfjprog --eraseuicr`."
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);
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#[cfg(feature = "reset-pin-as-gpio")]
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warn!(
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"You have requested using the reset pin as GPIO, by enabling the Cargo feature `reset-pin-as-gpio`.\n\
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However, UICR is already programmed to some other setting, and can't be changed without erasing it.\n\
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To fix this, erase UICR manually, for example using `probe-rs-cli erase` or `nrfjprog --eraseuicr`."
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);
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}
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}
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#[cfg(any(feature = "_nrf52", feature = "_nrf5340-app"))]
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unsafe {
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let value = if cfg!(feature = "nfc-pins-as-gpio") { 0 } else { !0 };
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let res = uicr_write(consts::UICR_NFCPINS, value);
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needs_reset |= res == WriteResult::Written;
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if res == WriteResult::Failed {
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// with nfc-pins-as-gpio, this can never fail because we're writing all zero bits.
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#[cfg(not(feature = "nfc-pins-as-gpio"))]
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warn!(
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"You have requested to use P0.09 and P0.10 pins for NFC, by not enabling the Cargo feature `nfc-pins-as-gpio`.\n\
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However, UICR is already programmed to some other setting, and can't be changed without erasing it.\n\
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To fix this, erase UICR manually, for example using `probe-rs-cli erase` or `nrfjprog --eraseuicr`."
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);
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}
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}
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if needs_reset {
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cortex_m::peripheral::SCB::sys_reset();
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}
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let r = unsafe { &*pac::CLOCK::ptr() };
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// Start HFCLK.
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match config.hfclk_source {
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config::HfclkSource::Internal => {}
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config::HfclkSource::ExternalXtal => {
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// Datasheet says this is likely to take 0.36ms
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r.events_hfclkstarted.write(|w| unsafe { w.bits(0) });
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r.tasks_hfclkstart.write(|w| unsafe { w.bits(1) });
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while r.events_hfclkstarted.read().bits() == 0 {}
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}
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}
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// Configure LFCLK.
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#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
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match config.lfclk_source {
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config::LfclkSource::InternalRC => r.lfclksrc.write(|w| w.src().rc()),
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config::LfclkSource::Synthesized => r.lfclksrc.write(|w| w.src().synth()),
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config::LfclkSource::ExternalXtal => r.lfclksrc.write(|w| w.src().xtal()),
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config::LfclkSource::ExternalLowSwing => r.lfclksrc.write(|w| {
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w.src().xtal();
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w.external().enabled();
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w.bypass().disabled();
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w
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}),
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config::LfclkSource::ExternalFullSwing => r.lfclksrc.write(|w| {
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w.src().xtal();
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w.external().enabled();
|
|
w.bypass().enabled();
|
|
w
|
|
}),
|
|
}
|
|
#[cfg(feature = "_nrf9160")]
|
|
match config.lfclk_source {
|
|
config::LfclkSource::InternalRC => r.lfclksrc.write(|w| w.src().lfrc()),
|
|
config::LfclkSource::ExternalXtal => r.lfclksrc.write(|w| w.src().lfxo()),
|
|
}
|
|
|
|
// Start LFCLK.
|
|
// Datasheet says this could take 100us from synth source
|
|
// 600us from rc source, 0.25s from an external source.
|
|
r.events_lfclkstarted.write(|w| unsafe { w.bits(0) });
|
|
r.tasks_lfclkstart.write(|w| unsafe { w.bits(1) });
|
|
while r.events_lfclkstarted.read().bits() == 0 {}
|
|
|
|
// Init GPIOTE
|
|
#[cfg(feature = "gpiote")]
|
|
gpiote::init(config.gpiote_interrupt_priority);
|
|
|
|
// init RTC time driver
|
|
#[cfg(feature = "_time-driver")]
|
|
time_driver::init(config.time_interrupt_priority);
|
|
|
|
// Disable UARTE (enabled by default for some reason)
|
|
#[cfg(feature = "_nrf9160")]
|
|
unsafe {
|
|
(*pac::UARTE0::ptr()).enable.write(|w| w.enable().disabled());
|
|
(*pac::UARTE1::ptr()).enable.write(|w| w.enable().disabled());
|
|
}
|
|
|
|
peripherals
|
|
}
|