432 lines
13 KiB
Rust
432 lines
13 KiB
Rust
// The v1c ethernet driver was ported to embassy from the awesome stm32-eth project (https://github.com/stm32-rs/stm32-eth).
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mod rx_desc;
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mod tx_desc;
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use core::marker::PhantomData;
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use core::sync::atomic::{fence, Ordering};
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use embassy_hal_internal::Peri;
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use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
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pub(crate) use self::rx_desc::{RDes, RDesRing};
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pub(crate) use self::tx_desc::{TDes, TDesRing};
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use super::*;
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#[cfg(eth_v1a)]
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use crate::gpio::Pull;
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use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
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use crate::interrupt;
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use crate::interrupt::InterruptExt;
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#[cfg(eth_v1a)]
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use crate::pac::AFIO;
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#[cfg(any(eth_v1b, eth_v1c))]
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use crate::pac::SYSCFG;
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use crate::pac::{ETH, RCC};
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use crate::rcc::SealedRccPeripheral;
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/// Interrupt handler.
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pub struct InterruptHandler {}
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impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandler {
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unsafe fn on_interrupt() {
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WAKER.wake();
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// TODO: Check and clear more flags
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let dma = ETH.ethernet_dma();
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dma.dmasr().modify(|w| {
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w.set_ts(true);
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w.set_rs(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmasr().read();
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dma.dmasr().read();
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}
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}
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/// Ethernet driver.
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pub struct Ethernet<'d, T: Instance, P: Phy> {
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_peri: Peri<'d, T>,
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pub(crate) tx: TDesRing<'d>,
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pub(crate) rx: RDesRing<'d>,
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pins: Pins<'d>,
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pub(crate) phy: P,
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pub(crate) station_management: EthernetStationManagement<T>,
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pub(crate) mac_addr: [u8; 6],
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}
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/// Pins of ethernet driver.
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enum Pins<'d> {
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Rmii([Peri<'d, AnyPin>; 9]),
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Mii([Peri<'d, AnyPin>; 14]),
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}
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#[cfg(eth_v1a)]
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macro_rules! config_in_pins {
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($($pin:ident),*) => {
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critical_section::with(|_| {
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$(
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// TODO properly create a set_as_input function
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$pin.set_as_af($pin.af_num(), AfType::input(Pull::None));
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)*
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})
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}
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}
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#[cfg(eth_v1a)]
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macro_rules! config_af_pins {
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($($pin:ident),*) => {
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critical_section::with(|_| {
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$(
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$pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
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)*
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})
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};
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}
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#[cfg(any(eth_v1b, eth_v1c))]
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macro_rules! config_pins {
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($($pin:ident),*) => {
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critical_section::with(|_| {
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$(
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$pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
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)*
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})
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};
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}
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impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
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/// safety: the returned instance is not leak-safe
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pub fn new<const TX: usize, const RX: usize>(
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queue: &'d mut PacketQueue<TX, RX>,
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peri: Peri<'d, T>,
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irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
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ref_clk: Peri<'d, impl RefClkPin<T>>,
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mdio: Peri<'d, impl MDIOPin<T>>,
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mdc: Peri<'d, impl MDCPin<T>>,
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crs: Peri<'d, impl CRSPin<T>>,
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rx_d0: Peri<'d, impl RXD0Pin<T>>,
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rx_d1: Peri<'d, impl RXD1Pin<T>>,
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tx_d0: Peri<'d, impl TXD0Pin<T>>,
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tx_d1: Peri<'d, impl TXD1Pin<T>>,
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tx_en: Peri<'d, impl TXEnPin<T>>,
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phy: P,
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mac_addr: [u8; 6],
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) -> Self {
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// Enable the necessary Clocks
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#[cfg(eth_v1a)]
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critical_section::with(|_| {
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RCC.apb2enr().modify(|w| w.set_afioen(true));
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// Select RMII (Reduced Media Independent Interface)
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// Must be done prior to enabling peripheral clock
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AFIO.mapr().modify(|w| w.set_mii_rmii_sel(true));
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RCC.ahbenr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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});
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#[cfg(any(eth_v1b, eth_v1c))]
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critical_section::with(|_| {
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RCC.ahb1enr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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// RMII (Reduced Media Independent Interface)
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SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(true));
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});
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#[cfg(eth_v1a)]
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{
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config_in_pins!(ref_clk, rx_d0, rx_d1);
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config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_en);
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}
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#[cfg(any(eth_v1b, eth_v1c))]
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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let pins = Pins::Rmii([
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ref_clk.into(),
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mdio.into(),
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mdc.into(),
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crs.into(),
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rx_d0.into(),
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rx_d1.into(),
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tx_d0.into(),
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tx_d1.into(),
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tx_en.into(),
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]);
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Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
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}
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fn new_inner<const TX: usize, const RX: usize>(
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queue: &'d mut PacketQueue<TX, RX>,
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peri: Peri<'d, T>,
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_irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
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pins: Pins<'d>,
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phy: P,
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mac_addr: [u8; 6],
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) -> Self {
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let dma = T::regs().ethernet_dma();
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let mac = T::regs().ethernet_mac();
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// Reset and wait
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dma.dmabmr().modify(|w| w.set_sr(true));
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while dma.dmabmr().read().sr() {}
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mac.maccr().modify(|w| {
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w.set_ifg(Ifg::IFG96); // inter frame gap 96 bit times
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w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping
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w.set_fes(Fes::FES100); // fast ethernet speed
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w.set_dm(Dm::FULL_DUPLEX); // full duplex
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// TODO: Carrier sense ? ECRSFD
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});
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// Set the mac to pass all multicast packets
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mac.macffr().modify(|w| {
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w.set_pam(true);
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});
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// Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
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// so the LR write must happen after the HR write.
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mac.maca0hr()
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.modify(|w| w.set_maca0h(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
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mac.maca0lr().write(|w| {
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w.set_maca0l(
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u32::from(mac_addr[0])
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| (u32::from(mac_addr[1]) << 8)
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| (u32::from(mac_addr[2]) << 16)
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| (u32::from(mac_addr[3]) << 24),
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)
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});
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// pause time
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mac.macfcr().modify(|w| w.set_pt(0x100));
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// Transfer and Forward, Receive and Forward
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dma.dmaomr().modify(|w| {
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w.set_tsf(Tsf::STORE_FORWARD);
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w.set_rsf(Rsf::STORE_FORWARD);
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});
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dma.dmabmr().modify(|w| {
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w.set_pbl(Pbl::PBL32) // programmable burst length - 32 ?
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});
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// TODO MTU size setting not found for v1 ethernet, check if correct
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let hclk = <T as SealedRccPeripheral>::frequency();
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let hclk_mhz = hclk.0 / 1_000_000;
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// Set the MDC clock frequency in the range 1MHz - 2.5MHz
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let clock_range = match hclk_mhz {
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0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."),
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25..=34 => Cr::CR_20_35, // Divide by 16
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35..=59 => Cr::CR_35_60, // Divide by 26
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60..=99 => Cr::CR_60_100, // Divide by 42
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100..=149 => Cr::CR_100_150, // Divide by 62
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150..=216 => Cr::CR_150_168, // Divide by 102
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_ => {
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panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
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}
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};
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let mut this = Self {
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_peri: peri,
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pins,
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phy: phy,
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station_management: EthernetStationManagement {
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peri: PhantomData,
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clock_range: clock_range,
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},
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mac_addr,
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tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
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rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
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};
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fence(Ordering::SeqCst);
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let mac = T::regs().ethernet_mac();
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let dma = T::regs().ethernet_dma();
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mac.maccr().modify(|w| {
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w.set_re(true);
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w.set_te(true);
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});
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dma.dmaomr().modify(|w| {
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w.set_ftf(Ftf::FLUSH); // flush transmit fifo (queue)
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w.set_st(St::STARTED); // start transmitting channel
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w.set_sr(DmaomrSr::STARTED); // start receiving channel
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});
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this.rx.demand_poll();
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// Enable interrupts
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dma.dmaier().modify(|w| {
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w.set_nise(true);
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w.set_rie(true);
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w.set_tie(true);
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});
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this.phy.phy_reset(&mut this.station_management);
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this.phy.phy_init(&mut this.station_management);
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interrupt::ETH.unpend();
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unsafe { interrupt::ETH.enable() };
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this
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}
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/// Create a new MII ethernet driver using 14 pins.
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pub fn new_mii<const TX: usize, const RX: usize>(
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queue: &'d mut PacketQueue<TX, RX>,
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peri: Peri<'d, T>,
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irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
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rx_clk: Peri<'d, impl RXClkPin<T>>,
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tx_clk: Peri<'d, impl TXClkPin<T>>,
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mdio: Peri<'d, impl MDIOPin<T>>,
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mdc: Peri<'d, impl MDCPin<T>>,
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rxdv: Peri<'d, impl RXDVPin<T>>,
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rx_d0: Peri<'d, impl RXD0Pin<T>>,
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rx_d1: Peri<'d, impl RXD1Pin<T>>,
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rx_d2: Peri<'d, impl RXD2Pin<T>>,
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rx_d3: Peri<'d, impl RXD3Pin<T>>,
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tx_d0: Peri<'d, impl TXD0Pin<T>>,
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tx_d1: Peri<'d, impl TXD1Pin<T>>,
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tx_d2: Peri<'d, impl TXD2Pin<T>>,
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tx_d3: Peri<'d, impl TXD3Pin<T>>,
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tx_en: Peri<'d, impl TXEnPin<T>>,
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phy: P,
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mac_addr: [u8; 6],
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) -> Self {
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// TODO: Handle optional signals like CRS, MII_COL, RX_ER?
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// Enable the necessary Clocks
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#[cfg(eth_v1a)]
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critical_section::with(|_| {
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RCC.apb2enr().modify(|w| w.set_afioen(true));
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// Select MII (Media Independent Interface)
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// Must be done prior to enabling peripheral clock
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AFIO.mapr().modify(|w| w.set_mii_rmii_sel(false));
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RCC.ahbenr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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});
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#[cfg(any(eth_v1b, eth_v1c))]
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critical_section::with(|_| {
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RCC.ahb1enr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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// MII (Media Independent Interface)
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SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(false));
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});
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#[cfg(eth_v1a)]
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{
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config_in_pins!(rx_clk, tx_clk, rx_d0, rx_d1, rx_d2, rx_d3, rxdv);
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config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
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}
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#[cfg(any(eth_v1b, eth_v1c))]
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config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
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let pins = Pins::Mii([
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rx_clk.into(),
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tx_clk.into(),
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mdio.into(),
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mdc.into(),
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rxdv.into(),
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rx_d0.into(),
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rx_d1.into(),
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rx_d2.into(),
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rx_d3.into(),
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tx_d0.into(),
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tx_d1.into(),
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tx_d2.into(),
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tx_d3.into(),
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tx_en.into(),
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]);
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Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
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}
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}
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/// Ethernet station management interface.
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pub(crate) struct EthernetStationManagement<T: Instance> {
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peri: PhantomData<T>,
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clock_range: Cr,
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}
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impl<T: Instance> StationManagement for EthernetStationManagement<T> {
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fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
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let mac = T::regs().ethernet_mac();
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mac.macmiiar().modify(|w| {
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w.set_pa(phy_addr);
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w.set_mr(reg);
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w.set_mw(Mw::READ); // read operation
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w.set_cr(self.clock_range);
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w.set_mb(MbProgress::BUSY); // indicate that operation is in progress
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});
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while mac.macmiiar().read().mb() == MbProgress::BUSY {}
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mac.macmiidr().read().md()
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}
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fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
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let mac = T::regs().ethernet_mac();
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mac.macmiidr().write(|w| w.set_md(val));
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mac.macmiiar().modify(|w| {
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w.set_pa(phy_addr);
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w.set_mr(reg);
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w.set_mw(Mw::WRITE); // write
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w.set_cr(self.clock_range);
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w.set_mb(MbProgress::BUSY);
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});
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while mac.macmiiar().read().mb() == MbProgress::BUSY {}
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}
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}
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impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> {
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fn drop(&mut self) {
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let dma = T::regs().ethernet_dma();
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let mac = T::regs().ethernet_mac();
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// Disable the TX DMA and wait for any previous transmissions to be completed
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dma.dmaomr().modify(|w| w.set_st(St::STOPPED));
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// Disable MAC transmitter and receiver
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mac.maccr().modify(|w| {
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w.set_re(false);
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w.set_te(false);
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});
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dma.dmaomr().modify(|w| w.set_sr(DmaomrSr::STOPPED));
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critical_section::with(|_| {
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for pin in match self.pins {
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Pins::Rmii(ref mut pins) => pins.iter_mut(),
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Pins::Mii(ref mut pins) => pins.iter_mut(),
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} {
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pin.set_as_disconnected();
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}
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})
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}
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}
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