404 lines
10 KiB
Rust
404 lines
10 KiB
Rust
#![macro_use]
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//! I2S
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use core::future::poll_fn;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use pac::i2s::config::mcken;
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use crate::{pac, Peripheral};
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use crate::interrupt::{Interrupt, InterruptExt};
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use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
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use crate::gpio::sealed::Pin as _;
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// TODO: Define those in lib.rs somewhere else
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//
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// I2S EasyDMA MAXCNT bit length = 14
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const MAX_DMA_MAXCNT: u32 = 1 << 14;
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// Limits for Easy DMA - it can only read from data ram
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pub const SRAM_LOWER: usize = 0x2000_0000;
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pub const SRAM_UPPER: usize = 0x3000_0000;
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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BufferTooLong,
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BufferZeroLength,
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DMABufferNotInDataMemory,
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BufferMisaligned,
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// TODO: add other error variants.
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}
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#[derive(Clone)]
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#[non_exhaustive]
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pub struct Config {
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pub ratio: Ratio,
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pub sample_width: SampleWidth,
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pub align: Align,
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pub format: Format,
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pub channels: Channels,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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ratio: Ratio::_32x,
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sample_width: SampleWidth::_16bit,
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align: Align::Left,
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format: Format::I2S,
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channels: Channels::Stereo,
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}
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}
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}
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/// MCK / LRCK ratio.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Ratio {
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_32x,
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_48x,
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_64x,
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_96x,
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_128x,
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_192x,
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_256x,
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_384x,
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_512x,
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}
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impl From<Ratio> for u8 {
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fn from(variant: Ratio) -> Self {
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variant as _
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}
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}
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum SampleWidth {
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_8bit,
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_16bit,
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_24bit,
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}
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impl From<SampleWidth> for u8 {
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fn from(variant: SampleWidth) -> Self {
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variant as _
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}
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}
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/// Alignment of sample within a frame.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Align {
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Left,
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Right,
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}
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impl From<Align> for bool {
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fn from(variant: Align) -> Self {
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match variant {
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Align::Left => false,
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Align::Right => true,
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}
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}
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}
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/// Frame format.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Format {
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I2S,
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Aligned,
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}
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impl From<Format> for bool {
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fn from(variant: Format) -> Self {
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match variant {
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Format::I2S => false,
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Format::Aligned => true,
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}
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}
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}
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/// Enable channels.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Channels {
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Stereo,
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Left,
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Right,
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}
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impl From<Channels> for u8 {
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fn from(variant: Channels) -> Self {
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variant as _
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}
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}
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/// I2S Mode
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Mode {
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Controller,
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Peripheral,
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}
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// /// Master clock generator frequency.
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// #[derive(Debug, Eq, PartialEq, Clone, Copy)]
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// pub enum MckFreq {
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// _32MDiv8 = 0x20000000,
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// _32MDiv10 = 0x18000000,
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// _32MDiv11 = 0x16000000,
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// _32MDiv15 = 0x11000000,
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// _32MDiv16 = 0x10000000,
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// _32MDiv21 = 0x0C000000,
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// _32MDiv23 = 0x0B000000,
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// _32MDiv30 = 0x08800000,
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// _32MDiv31 = 0x08400000,
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// _32MDiv32 = 0x08000000,
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// _32MDiv42 = 0x06000000,
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// _32MDiv63 = 0x04100000,
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// _32MDiv125 = 0x020C0000,
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// }
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/// Interface to the UARTE peripheral using EasyDMA to offload the transmission and reception workload.
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///
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/// For more details about EasyDMA, consult the module documentation.
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pub struct I2s<'d, T: Instance> {
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output: I2sOutput<'d, T>,
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input: I2sInput<'d, T>,
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}
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/// Transmitter interface to the UARTE peripheral obtained
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/// via [Uarte]::split.
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pub struct I2sOutput<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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/// Receiver interface to the UARTE peripheral obtained
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/// via [Uarte]::split.
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pub struct I2sInput<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance> I2s<'d, T> {
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/// Create a new I2S
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pub fn new(
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i2s: impl Peripheral<P = T> + 'd,
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// irq: impl Peripheral<P = T::Interrupt> + 'd,
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mck: impl Peripheral<P = impl GpioPin> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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lrck: impl Peripheral<P = impl GpioPin> + 'd,
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sdin: impl Peripheral<P = impl GpioPin> + 'd,
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sdout: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(mck, sck, lrck, sdin, sdout);
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Self::new_inner(
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i2s,
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// irq,
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mck.map_into(), sck.map_into(), lrck.map_into(), sdin.map_into(), sdout.map_into(), config)
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}
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fn new_inner(
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i2s: impl Peripheral<P = T> + 'd,
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// irq: impl Peripheral<P = T::Interrupt> + 'd,
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mck: PeripheralRef<'d, AnyPin>,
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sck: PeripheralRef<'d, AnyPin>,
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lrck: PeripheralRef<'d, AnyPin>,
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sdin: PeripheralRef<'d, AnyPin>,
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sdout: PeripheralRef<'d, AnyPin>,
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config: Config,
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) -> Self {
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into_ref!(
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i2s,
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// irq,
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mck, sck, lrck, sdin, sdout);
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let r = T::regs();
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// TODO get configuration rather than hardcoding ratio, swidth, align, format, channels
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r.config.mcken.write(|w| w.mcken().enabled());
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r.config.mckfreq.write(|w| w.mckfreq()._32mdiv16());
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r.config.ratio.write(|w| w.ratio()._192x());
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r.config.mode.write(|w| w.mode().master());
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r.config.swidth.write(|w| w.swidth()._16bit());
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r.config.align.write(|w| w.align().left());
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r.config.format.write(|w| w.format().i2s());
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r.config.channels.write(|w| w.channels().stereo());
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r.psel.mck.write(|w| {
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unsafe { w.bits(mck.psel_bits()) };
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w.connect().connected()
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});
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r.psel.sck.write(|w| {
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unsafe { w.bits(sck.psel_bits()) };
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w.connect().connected()
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});
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r.psel.lrck.write(|w| {
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unsafe { w.bits(lrck.psel_bits()) };
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w.connect().connected()
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});
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r.psel.sdin.write(|w| {
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unsafe { w.bits(sdin.psel_bits()) };
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w.connect().connected()
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});
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r.psel.sdout.write(|w| {
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unsafe { w.bits(sdout.psel_bits()) };
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w.connect().connected()
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});
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r.enable.write(|w| w.enable().enabled());
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Self {
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output: I2sOutput {
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_p: unsafe { i2s.clone_unchecked() },
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},
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input: I2sInput { _p: i2s },
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}
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}
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/// Enables the I2S module.
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#[inline(always)]
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pub fn enable(&self) -> &Self {
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let r = T::regs();
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r.enable.write(|w| w.enable().enabled());
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self
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}
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/// Disables the I2S module.
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#[inline(always)]
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pub fn disable(&self) -> &Self {
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let r = T::regs();
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r.enable.write(|w| w.enable().disabled());
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self
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}
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/// Starts I2S transfer.
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#[inline(always)]
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pub fn start(&self) -> &Self {
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let r = T::regs();
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self.enable();
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r.tasks_start.write(|w| unsafe { w.bits(1) });
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self
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}
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/// Stops the I2S transfer and waits until it has stopped.
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#[inline(always)]
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pub fn stop(&self) -> &Self {
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todo!()
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}
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/// Enables/disables I2S transmission (TX).
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#[inline(always)]
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pub fn set_tx_enabled(&self, enabled: bool) -> &Self {
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let r = T::regs();
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r.config.txen.write(|w| w.txen().bit(enabled));
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self
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}
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/// Enables/disables I2S reception (RX).
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#[inline(always)]
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pub fn set_rx_enabled(&self, enabled: bool) -> &Self {
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let r = T::regs();
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r.config.rxen.write(|w| w.rxen().bit(enabled));
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self
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}
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/// Transmits the given `tx_buffer`.
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/// Buffer address must be 4 byte aligned and located in RAM.
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/// Returns a value that represents the in-progress DMA transfer.
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// TODO Define a better interface for the input buffer
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#[allow(unused_mut)]
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pub async fn tx(&mut self, ptr: *const u8, len: usize) -> Result<(), Error> {
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self.output.tx(ptr, len).await
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}
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}
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impl<'d, T: Instance> I2sOutput<'d, T> {
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/// Transmits the given `tx_buffer`.
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/// Buffer address must be 4 byte aligned and located in RAM.
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/// Returns a value that represents the in-progress DMA transfer.
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// TODO Define a better interface for the input buffer
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pub async fn tx(&mut self, ptr: *const u8, len: usize) -> Result<(), Error> {
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if ptr as u32 % 4 != 0 {
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return Err(Error::BufferMisaligned);
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}
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let maxcnt = (len / (core::mem::size_of::<u32>() / core::mem::size_of::<u8>())) as u32;
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if maxcnt > MAX_DMA_MAXCNT {
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return Err(Error::BufferTooLong);
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}
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if (ptr as usize) < SRAM_LOWER || (ptr as usize) > SRAM_UPPER {
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return Err(Error::DMABufferNotInDataMemory);
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}
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let r = T::regs();
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let _s = T::state();
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// TODO we can not progress until the last buffer written in TXD.PTR
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// has started the transmission.
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// We can use some sync primitive from `embassy-sync`.
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxtxd.maxcnt.write(|w| unsafe { w.bits(maxcnt) });
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Ok(())
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}
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}
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pub(crate) mod sealed {
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use core::sync::atomic::AtomicU8;
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use embassy_sync::waitqueue::AtomicWaker;
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use super::*;
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pub struct State {
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pub input_waker: AtomicWaker,
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pub output_waker: AtomicWaker,
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pub buffers_refcount: AtomicU8,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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input_waker: AtomicWaker::new(),
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output_waker: AtomicWaker::new(),
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buffers_refcount: AtomicU8::new(0),
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}
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}
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}
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pub trait Instance {
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fn regs() -> &'static pac::i2s::RegisterBlock;
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fn state() -> &'static State;
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}
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}
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pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
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type Interrupt: Interrupt;
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}
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macro_rules! impl_i2s {
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($type:ident, $pac_type:ident, $irq:ident) => {
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impl crate::i2s::sealed::Instance for peripherals::$type {
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fn regs() -> &'static pac::i2s::RegisterBlock {
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unsafe { &*pac::$pac_type::ptr() }
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}
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fn state() -> &'static crate::i2s::sealed::State {
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static STATE: crate::i2s::sealed::State = crate::i2s::sealed::State::new();
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&STATE
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}
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}
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impl crate::i2s::Instance for peripherals::$type {
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type Interrupt = crate::interrupt::$irq;
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}
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};
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}
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