803 lines
22 KiB
Rust
803 lines
22 KiB
Rust
use std::cmp::Ordering;
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use std::collections::{BTreeSet, HashMap};
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use std::io::Write;
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use std::path::{Path, PathBuf};
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use std::process::Command;
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use std::sync::LazyLock;
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use std::{env, fs};
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use common::CfgSet;
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use mspm0_metapac::metadata::METADATA;
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use proc_macro2::{Ident, Literal, Span, TokenStream};
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use quote::{format_ident, quote};
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#[path = "./build_common.rs"]
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mod common;
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fn main() {
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generate_code();
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}
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fn generate_code() {
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let mut cfgs = common::CfgSet::new();
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common::set_target_cfgs(&mut cfgs);
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cfgs.declare_all(&["gpio_pb", "gpio_pc", "int_group1"]);
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let mut singletons = get_singletons(&mut cfgs);
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time_driver(&mut singletons, &mut cfgs);
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let mut g = TokenStream::new();
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g.extend(generate_singletons(&singletons));
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g.extend(generate_pincm_mapping());
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g.extend(generate_pin());
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g.extend(generate_timers());
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g.extend(generate_interrupts());
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g.extend(generate_peripheral_instances());
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g.extend(generate_pin_trait_impls());
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let out_dir = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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let out_file = out_dir.join("_generated.rs").to_string_lossy().to_string();
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fs::write(&out_file, g.to_string()).unwrap();
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rustfmt(&out_file);
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}
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#[derive(Debug, Clone)]
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struct Singleton {
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name: String,
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cfg: Option<TokenStream>,
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}
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impl PartialEq for Singleton {
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fn eq(&self, other: &Self) -> bool {
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self.name == other.name
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}
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}
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impl Eq for Singleton {}
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impl PartialOrd for Singleton {
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fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
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Some(self.cmp(other))
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}
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}
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impl Ord for Singleton {
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fn cmp(&self, other: &Self) -> Ordering {
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self.name.cmp(&other.name)
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}
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}
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fn get_singletons(cfgs: &mut common::CfgSet) -> Vec<Singleton> {
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let mut singletons = Vec::<Singleton>::new();
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for peripheral in METADATA.peripherals {
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// Some peripherals do not generate a singleton, but generate a singleton for each pin.
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let skip_peripheral_singleton = match peripheral.kind {
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"gpio" => {
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// Also enable ports that are present.
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match peripheral.name {
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"GPIOB" => cfgs.enable("gpio_pb"),
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"GPIOC" => cfgs.enable("gpio_pc"),
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_ => (),
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}
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true
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}
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// Each channel gets a singleton, handled separately.
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"dma" => true,
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// These peripherals do not exist as singletons, and have no signals but are managed
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// by the HAL.
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"iomux" | "cpuss" => true,
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_ => false,
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};
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if !skip_peripheral_singleton {
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singletons.push(Singleton {
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name: peripheral.name.to_string(),
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cfg: None,
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});
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}
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let mut signals = BTreeSet::new();
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// Pick out each unique signal. There may be multiple instances of each signal due to
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// iomux mappings.
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for pin in peripheral.pins {
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let signal = if peripheral.name.starts_with("GPIO")
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|| peripheral.name.starts_with("VREF")
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|| peripheral.name.starts_with("RTC")
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{
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pin.signal.to_string()
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} else {
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format!("{}_{}", peripheral.name, pin.signal)
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};
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// We need to rename some signals to become valid Rust identifiers.
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let signal = make_valid_identifier(&signal);
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signals.insert(signal);
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}
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singletons.extend(signals);
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}
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// DMA channels get their own singletons
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for dma_channel in METADATA.dma_channels.iter() {
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singletons.push(Singleton {
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name: format!("DMA_CH{}", dma_channel.number),
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cfg: None,
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});
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}
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singletons.sort_by(|a, b| a.name.cmp(&b.name));
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singletons
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}
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fn make_valid_identifier(s: &str) -> Singleton {
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let name = s.replace('+', "_P").replace("-", "_N");
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Singleton { name, cfg: None }
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}
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fn generate_pincm_mapping() -> TokenStream {
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let pincms = METADATA.pincm_mappings.iter().map(|mapping| {
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let port_letter = mapping.pin.strip_prefix("P").unwrap();
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let port_base = (port_letter.chars().next().unwrap() as u8 - b'A') * 32;
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// This assumes all ports are single letter length.
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// This is fine unless TI releases a part with 833+ GPIO pins.
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let pin_number = mapping.pin[2..].parse::<u8>().unwrap();
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let num = port_base + pin_number;
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// But subtract 1 since pincm indices start from 0, not 1.
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let pincm = Literal::u8_unsuffixed(mapping.pincm - 1);
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quote! {
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#num => #pincm
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}
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});
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quote! {
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#[doc = "Get the mapping from GPIO pin port to IOMUX PINCM index. This is required since the mapping from IO to PINCM index is not consistent across parts."]
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pub(crate) fn gpio_pincm(pin_port: u8) -> u8 {
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match pin_port {
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#(#pincms),*,
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_ => unreachable!(),
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}
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}
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}
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}
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fn generate_pin() -> TokenStream {
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let pin_impls = METADATA.pincm_mappings.iter().map(|pincm_mapping| {
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let name = Ident::new(&pincm_mapping.pin, Span::call_site());
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let port_letter = pincm_mapping.pin.strip_prefix("P").unwrap();
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let port_letter = port_letter.chars().next().unwrap();
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let pin_number = Literal::u8_unsuffixed(pincm_mapping.pin[2..].parse::<u8>().unwrap());
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let port = Ident::new(&format!("Port{}", port_letter), Span::call_site());
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// TODO: Feature gate pins that can be used as NRST
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quote! {
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impl_pin!(#name, crate::gpio::Port::#port, #pin_number);
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}
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});
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quote! {
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#(#pin_impls)*
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}
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}
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fn time_driver(singletons: &mut Vec<Singleton>, cfgs: &mut CfgSet) {
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// Timer features
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for (timer, _) in TIMERS.iter() {
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let name = timer.to_lowercase();
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cfgs.declare(&format!("time_driver_{}", name));
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}
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let time_driver = match env::vars()
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.map(|(a, _)| a)
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.filter(|x| x.starts_with("CARGO_FEATURE_TIME_DRIVER_"))
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.get_one()
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{
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Ok(x) => Some(
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x.strip_prefix("CARGO_FEATURE_TIME_DRIVER_")
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.unwrap()
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.to_ascii_lowercase(),
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),
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Err(GetOneError::None) => None,
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Err(GetOneError::Multiple) => panic!("Multiple time-driver-xxx Cargo features enabled"),
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};
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// Verify the selected timer is available
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let selected_timer = match time_driver.as_ref().map(|x| x.as_ref()) {
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None => "",
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Some("timg0") => "TIMG0",
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Some("timg1") => "TIMG1",
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Some("timg2") => "TIMG2",
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Some("timg3") => "TIMG3",
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Some("timg4") => "TIMG4",
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Some("timg5") => "TIMG5",
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Some("timg6") => "TIMG6",
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Some("timg7") => "TIMG7",
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Some("timg8") => "TIMG8",
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Some("timg9") => "TIMG9",
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Some("timg10") => "TIMG10",
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Some("timg11") => "TIMG11",
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Some("timg14") => "TIMG14",
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Some("tima0") => "TIMA0",
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Some("tima1") => "TIMA1",
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Some("any") => {
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// Order of timer candidates:
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// 1. 16-bit, 2 channel
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// 2. 16-bit, 2 channel with shadow registers
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// 3. 16-bit, 4 channel
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// 4. 16-bit with QEI
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// 5. Advanced timers
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//
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// TODO: Select RTC first if available
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// TODO: 32-bit timers are not considered yet
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[
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// 16-bit, 2 channel
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"TIMG0", "TIMG1", "TIMG2", "TIMG3", // 16-bit, 2 channel with shadow registers
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"TIMG4", "TIMG5", "TIMG6", "TIMG7", // 16-bit, 4 channel
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"TIMG14", // 16-bit with QEI
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"TIMG8", "TIMG9", "TIMG10", "TIMG11", // Advanced timers
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"TIMA0", "TIMA1",
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]
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.iter()
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.find(|tim| singletons.iter().any(|s| s.name == **tim))
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.expect("Could not find any timer")
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}
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_ => panic!("unknown time_driver {:?}", time_driver),
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};
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if !selected_timer.is_empty() {
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cfgs.enable(format!("time_driver_{}", selected_timer.to_lowercase()));
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}
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// Apply cfgs to each timer and it's pins
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for singleton in singletons.iter_mut() {
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if singleton.name.starts_with("TIM") {
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// Remove suffixes for pin singletons.
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let name = if singleton.name.contains("_CCP") {
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singleton.name.split_once("_CCP").unwrap().0
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} else if singleton.name.contains("_FAULT") {
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singleton.name.split_once("_FAULT").unwrap().0
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} else if singleton.name.contains("_IDX") {
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singleton.name.split_once("_IDX").unwrap().0
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} else {
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&singleton.name
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};
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let feature = format!("time-driver-{}", name.to_lowercase());
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if singleton.name.contains(selected_timer) {
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singleton.cfg = Some(quote! { #[cfg(not(all(feature = "time-driver-any", feature = #feature)))] });
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} else {
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singleton.cfg = Some(quote! { #[cfg(not(feature = #feature))] });
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}
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}
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}
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}
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fn generate_singletons(singletons: &[Singleton]) -> TokenStream {
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let singletons = singletons
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.iter()
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.map(|s| {
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let cfg = s.cfg.clone().unwrap_or_default();
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let ident = format_ident!("{}", s.name);
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quote! {
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#cfg
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#ident
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}
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})
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.collect::<Vec<_>>();
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quote! {
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embassy_hal_internal::peripherals_definition!(#(#singletons),*);
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embassy_hal_internal::peripherals_struct!(#(#singletons),*);
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}
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}
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fn generate_timers() -> TokenStream {
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// Generate timers
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let timer_impls = METADATA
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.peripherals
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.iter()
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.filter(|p| p.name.starts_with("TIM"))
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.map(|peripheral| {
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let name = Ident::new(&peripheral.name, Span::call_site());
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let timers = &*TIMERS;
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let timer = timers.get(peripheral.name).expect("Timer does not exist");
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assert!(timer.bits == 16 || timer.bits == 32);
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let bits = if timer.bits == 16 {
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quote! { Bits16 }
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} else {
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quote! { Bits32 }
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};
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quote! {
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impl_timer!(#name, #bits);
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}
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});
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quote! {
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#(#timer_impls)*
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}
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}
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fn generate_interrupts() -> TokenStream {
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// Generate interrupt module
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let interrupts: Vec<Ident> = METADATA
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.interrupts
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.iter()
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.map(|interrupt| Ident::new(interrupt.name, Span::call_site()))
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.collect();
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let group_interrupt_enables = METADATA
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.interrupts
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.iter()
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.filter(|interrupt| interrupt.name.contains("GROUP"))
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.map(|interrupt| {
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let name = Ident::new(interrupt.name, Span::call_site());
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quote! {
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crate::interrupt::typelevel::#name::enable();
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}
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});
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// Generate interrupt enables for groups
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quote! {
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embassy_hal_internal::interrupt_mod! {
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#(#interrupts),*
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}
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pub fn enable_group_interrupts(_cs: critical_section::CriticalSection) {
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use crate::interrupt::typelevel::Interrupt;
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unsafe {
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#(#group_interrupt_enables)*
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}
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}
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}
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}
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fn generate_peripheral_instances() -> TokenStream {
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let mut impls = Vec::<TokenStream>::new();
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for peripheral in METADATA.peripherals {
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let peri = format_ident!("{}", peripheral.name);
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// Will be filled in when uart implementation is finished
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let _ = peri;
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let tokens = match peripheral.kind {
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"uart" => Some(quote! { impl_uart_instance!(#peri); }),
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_ => None,
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};
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if let Some(tokens) = tokens {
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impls.push(tokens);
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}
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}
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quote! {
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#(#impls)*
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}
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}
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fn generate_pin_trait_impls() -> TokenStream {
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let mut impls = Vec::<TokenStream>::new();
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for peripheral in METADATA.peripherals {
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for pin in peripheral.pins {
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let key = (peripheral.kind, pin.signal);
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let pin_name = format_ident!("{}", pin.pin);
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let peri = format_ident!("{}", peripheral.name);
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let pf = pin.pf;
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// Will be filled in when uart implementation is finished
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let _ = pin_name;
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let _ = peri;
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let _ = pf;
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let tokens = match key {
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("uart", "TX") => Some(quote! { impl_uart_tx_pin!(#peri, #pin_name, #pf); }),
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("uart", "RX") => Some(quote! { impl_uart_rx_pin!(#peri, #pin_name, #pf); }),
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("uart", "CTS") => Some(quote! { impl_uart_cts_pin!(#peri, #pin_name, #pf); }),
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("uart", "RTS") => Some(quote! { impl_uart_rts_pin!(#peri, #pin_name, #pf); }),
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_ => None,
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};
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if let Some(tokens) = tokens {
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impls.push(tokens);
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}
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}
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}
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quote! {
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#(#impls)*
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}
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}
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/// rustfmt a given path.
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/// Failures are logged to stderr and ignored.
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fn rustfmt(path: impl AsRef<Path>) {
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let path = path.as_ref();
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match Command::new("rustfmt").args([path]).output() {
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Err(e) => {
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eprintln!("failed to exec rustfmt {:?}: {:?}", path, e);
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}
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Ok(out) => {
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if !out.status.success() {
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eprintln!("rustfmt {:?} failed:", path);
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eprintln!("=== STDOUT:");
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std::io::stderr().write_all(&out.stdout).unwrap();
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eprintln!("=== STDERR:");
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std::io::stderr().write_all(&out.stderr).unwrap();
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}
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}
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}
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}
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#[allow(dead_code)]
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struct TimerDesc {
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bits: u8,
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/// Is there an 8-bit prescaler
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prescaler: bool,
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/// Is there a repeat counter
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repeat_counter: bool,
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ccp_channels_internal: u8,
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ccp_channels_external: u8,
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external_pwm_channels: u8,
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phase_load: bool,
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shadow_load: bool,
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shadow_ccs: bool,
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deadband: bool,
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fault_handler: bool,
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qei_hall: bool,
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}
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/// Description of all timer instances.
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const TIMERS: LazyLock<HashMap<String, TimerDesc>> = LazyLock::new(|| {
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let mut map = HashMap::new();
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map.insert(
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"TIMG0".into(),
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TimerDesc {
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bits: 16,
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prescaler: true,
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repeat_counter: false,
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ccp_channels_internal: 2,
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ccp_channels_external: 2,
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external_pwm_channels: 2,
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phase_load: false,
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shadow_load: false,
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shadow_ccs: false,
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deadband: false,
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fault_handler: false,
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qei_hall: false,
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},
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);
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map.insert(
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"TIMG1".into(),
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TimerDesc {
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bits: 16,
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prescaler: true,
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repeat_counter: false,
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ccp_channels_internal: 2,
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ccp_channels_external: 2,
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external_pwm_channels: 2,
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phase_load: false,
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shadow_load: false,
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shadow_ccs: false,
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deadband: false,
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fault_handler: false,
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qei_hall: false,
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},
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);
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map.insert(
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"TIMG2".into(),
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TimerDesc {
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bits: 16,
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prescaler: true,
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repeat_counter: false,
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ccp_channels_internal: 2,
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ccp_channels_external: 2,
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external_pwm_channels: 2,
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phase_load: false,
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shadow_load: false,
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shadow_ccs: false,
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deadband: false,
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fault_handler: false,
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qei_hall: false,
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},
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);
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map.insert(
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"TIMG3".into(),
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TimerDesc {
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bits: 16,
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prescaler: true,
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repeat_counter: false,
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ccp_channels_internal: 2,
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ccp_channels_external: 2,
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external_pwm_channels: 2,
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phase_load: false,
|
|
shadow_load: false,
|
|
shadow_ccs: false,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG4".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: true,
|
|
shadow_ccs: true,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG5".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: true,
|
|
shadow_ccs: true,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG6".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: true,
|
|
shadow_ccs: true,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG7".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: true,
|
|
shadow_ccs: true,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG8".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: false,
|
|
shadow_ccs: false,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: true,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG9".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: false,
|
|
shadow_ccs: false,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: true,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG10".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: false,
|
|
shadow_ccs: false,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: true,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG11".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: false,
|
|
shadow_ccs: false,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: true,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG12".into(),
|
|
TimerDesc {
|
|
bits: 32,
|
|
prescaler: false,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: false,
|
|
shadow_ccs: true,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG13".into(),
|
|
TimerDesc {
|
|
bits: 32,
|
|
prescaler: false,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 2,
|
|
phase_load: false,
|
|
shadow_load: false,
|
|
shadow_ccs: true,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMG14".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: false,
|
|
ccp_channels_internal: 4,
|
|
ccp_channels_external: 4,
|
|
external_pwm_channels: 4,
|
|
phase_load: false,
|
|
shadow_load: false,
|
|
shadow_ccs: false,
|
|
deadband: false,
|
|
fault_handler: false,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMA0".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: true,
|
|
ccp_channels_internal: 4,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 8,
|
|
phase_load: true,
|
|
shadow_load: true,
|
|
shadow_ccs: true,
|
|
deadband: true,
|
|
fault_handler: true,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map.insert(
|
|
"TIMA1".into(),
|
|
TimerDesc {
|
|
bits: 16,
|
|
prescaler: true,
|
|
repeat_counter: true,
|
|
ccp_channels_internal: 2,
|
|
ccp_channels_external: 2,
|
|
external_pwm_channels: 4,
|
|
phase_load: true,
|
|
shadow_load: true,
|
|
shadow_ccs: true,
|
|
deadband: true,
|
|
fault_handler: true,
|
|
qei_hall: false,
|
|
},
|
|
);
|
|
|
|
map
|
|
});
|
|
|
|
enum GetOneError {
|
|
None,
|
|
Multiple,
|
|
}
|
|
|
|
trait IteratorExt: Iterator {
|
|
fn get_one(self) -> Result<Self::Item, GetOneError>;
|
|
}
|
|
|
|
impl<T: Iterator> IteratorExt for T {
|
|
fn get_one(mut self) -> Result<Self::Item, GetOneError> {
|
|
match self.next() {
|
|
None => Err(GetOneError::None),
|
|
Some(res) => match self.next() {
|
|
Some(_) => Err(GetOneError::Multiple),
|
|
None => Ok(res),
|
|
},
|
|
}
|
|
}
|
|
}
|