3916b26b25
This was likely forgotten as part of c46418f12. Without this, when creating a uarte instance, dropping it and then creating another instance, this instance would never receive any bytes.
716 lines
24 KiB
Rust
716 lines
24 KiB
Rust
//! Async buffered UART driver.
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//!
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//! Note that discarding a future from a read or write operation may lead to losing
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//! data. For example, when using `futures_util::future::select` and completion occurs
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//! on the "other" future, you should capture the incomplete future and continue to use
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//! it for the next read or write. This pattern is a consideration for all IO, and not
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//! just serial communications.
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//!
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//! Please also see [crate::uarte] to understand when [BufferedUarte] should be used.
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use core::cmp::min;
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::slice;
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use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU8, AtomicUsize, Ordering};
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use core::task::Poll;
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use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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// Re-export SVD variants to allow user to directly set values
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pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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use crate::gpio::sealed::Pin;
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use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
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use crate::interrupt::typelevel::Interrupt;
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use crate::ppi::{
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self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
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};
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use crate::timer::{Instance as TimerInstance, Timer};
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use crate::uarte::{apply_workaround_for_enable_anomaly, Config, Instance as UarteInstance};
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use crate::{interrupt, pac, Peripheral};
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mod sealed {
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use super::*;
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pub struct State {
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pub tx_waker: AtomicWaker,
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pub tx_buf: RingBuffer,
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pub tx_count: AtomicUsize,
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pub rx_waker: AtomicWaker,
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pub rx_buf: RingBuffer,
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pub rx_started: AtomicBool,
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pub rx_started_count: AtomicU8,
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pub rx_ended_count: AtomicU8,
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pub rx_ppi_ch: AtomicU8,
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}
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}
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/// UART error.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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// No errors for now
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}
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pub(crate) use sealed::State;
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impl State {
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pub(crate) const fn new() -> Self {
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Self {
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tx_waker: AtomicWaker::new(),
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tx_buf: RingBuffer::new(),
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tx_count: AtomicUsize::new(0),
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rx_waker: AtomicWaker::new(),
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rx_buf: RingBuffer::new(),
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rx_started: AtomicBool::new(false),
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rx_started_count: AtomicU8::new(0),
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rx_ended_count: AtomicU8::new(0),
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rx_ppi_ch: AtomicU8::new(0),
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}
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}
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}
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/// Interrupt handler.
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pub struct InterruptHandler<U: UarteInstance> {
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_phantom: PhantomData<U>,
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}
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impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for InterruptHandler<U> {
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unsafe fn on_interrupt() {
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//trace!("irq: start");
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let r = U::regs();
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let s = U::buffered_state();
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let buf_len = s.rx_buf.len();
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let half_len = buf_len / 2;
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let mut tx = unsafe { s.tx_buf.reader() };
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let mut rx = unsafe { s.rx_buf.writer() };
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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let errs = r.errorsrc.read();
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r.errorsrc.write(|w| unsafe { w.bits(errs.bits()) });
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if errs.overrun().bit() {
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panic!("BufferedUarte overrun");
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}
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}
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// Received some bytes, wake task.
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if r.inten.read().rxdrdy().bit_is_set() && r.events_rxdrdy.read().bits() != 0 {
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r.intenclr.write(|w| w.rxdrdy().clear());
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r.events_rxdrdy.reset();
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s.rx_waker.wake();
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}
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if r.events_endrx.read().bits() != 0 {
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//trace!(" irq_rx: endrx");
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r.events_endrx.reset();
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let val = s.rx_ended_count.load(Ordering::Relaxed);
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s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
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}
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if r.events_rxstarted.read().bits() != 0 || !s.rx_started.load(Ordering::Relaxed) {
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//trace!(" irq_rx: rxstarted");
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let (ptr, len) = rx.push_buf();
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if len >= half_len {
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r.events_rxstarted.reset();
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//trace!(" irq_rx: starting second {:?}", half_len);
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// Set up the DMA read
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
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let chn = s.rx_ppi_ch.load(Ordering::Relaxed);
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// Enable endrx -> startrx PPI channel.
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// From this point on, if endrx happens, startrx is automatically fired.
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ppi::regs().chenset.write(|w| unsafe { w.bits(1 << chn) });
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// It is possible that endrx happened BEFORE enabling the PPI. In this case
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// the PPI channel doesn't trigger, and we'd hang. We have to detect this
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// and manually start.
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// check again in case endrx has happened between the last check and now.
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if r.events_endrx.read().bits() != 0 {
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//trace!(" irq_rx: endrx");
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r.events_endrx.reset();
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let val = s.rx_ended_count.load(Ordering::Relaxed);
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s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
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}
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let rx_ended = s.rx_ended_count.load(Ordering::Relaxed);
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let rx_started = s.rx_started_count.load(Ordering::Relaxed);
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// If we started the same amount of transfers as ended, the last rxend has
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// already occured.
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let rxend_happened = rx_started == rx_ended;
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// Check if the PPI channel is still enabled. The PPI channel disables itself
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// when it fires, so if it's still enabled it hasn't fired.
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let ppi_ch_enabled = ppi::regs().chen.read().bits() & (1 << chn) != 0;
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// if rxend happened, and the ppi channel hasn't fired yet, the rxend got missed.
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// this condition also naturally matches if `!started`, needed to kickstart the DMA.
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if rxend_happened && ppi_ch_enabled {
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//trace!("manually starting.");
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// disable the ppi ch, it's of no use anymore.
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ppi::regs().chenclr.write(|w| unsafe { w.bits(1 << chn) });
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// manually start
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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}
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rx.push_done(half_len);
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s.rx_started_count.store(rx_started.wrapping_add(1), Ordering::Relaxed);
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s.rx_started.store(true, Ordering::Relaxed);
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} else {
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//trace!(" irq_rx: rxstarted no buf");
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r.intenclr.write(|w| w.rxstarted().clear());
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}
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}
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// =============================
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// TX end
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if r.events_endtx.read().bits() != 0 {
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r.events_endtx.reset();
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let n = s.tx_count.load(Ordering::Relaxed);
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//trace!(" irq_tx: endtx {:?}", n);
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tx.pop_done(n);
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s.tx_waker.wake();
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s.tx_count.store(0, Ordering::Relaxed);
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}
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// If not TXing, start.
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if s.tx_count.load(Ordering::Relaxed) == 0 {
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let (ptr, len) = tx.pop_buf();
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if len != 0 {
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//trace!(" irq_tx: starting {:?}", len);
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s.tx_count.store(len, Ordering::Relaxed);
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// Set up the DMA write
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Start UARTE Transmit transaction
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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}
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}
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//trace!("irq: end");
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}
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}
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/// Buffered UARTE driver.
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pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
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_peri: PeripheralRef<'d, U>,
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timer: Timer<'d, T>,
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_ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_group: PpiGroup<'d, AnyGroup>,
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}
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impl<'d, U: UarteInstance, T: TimerInstance> Unpin for BufferedUarte<'d, U, T> {}
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impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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/// Create a new BufferedUarte without hardware flow control.
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_group: impl Peripheral<P = impl Group> + 'd,
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_irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(rxd, txd, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1.map_into(),
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ppi_ch2.map_into(),
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ppi_group.map_into(),
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rxd.map_into(),
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txd.map_into(),
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None,
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None,
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config,
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rx_buffer,
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tx_buffer,
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)
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}
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/// Create a new BufferedUarte with hardware flow control (RTS/CTS)
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new_with_rtscts(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_group: impl Peripheral<P = impl Group> + 'd,
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_irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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cts: impl Peripheral<P = impl GpioPin> + 'd,
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rts: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(rxd, txd, cts, rts, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1.map_into(),
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ppi_ch2.map_into(),
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ppi_group.map_into(),
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rxd.map_into(),
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txd.map_into(),
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Some(cts.map_into()),
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Some(rts.map_into()),
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config,
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rx_buffer,
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tx_buffer,
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)
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}
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fn new_inner(
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peri: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_group: PeripheralRef<'d, AnyGroup>,
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rxd: PeripheralRef<'d, AnyPin>,
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txd: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(peri, timer);
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assert!(rx_buffer.len() % 2 == 0);
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let r = U::regs();
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let hwfc = cts.is_some();
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = &cts {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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if let Some(pin) = &rts {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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// Initialize state
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let s = U::buffered_state();
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s.tx_count.store(0, Ordering::Relaxed);
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s.rx_started_count.store(0, Ordering::Relaxed);
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s.rx_ended_count.store(0, Ordering::Relaxed);
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s.rx_started.store(false, Ordering::Relaxed);
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let len = tx_buffer.len();
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unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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// Configure
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r.config.write(|w| {
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w.hwfc().bit(hwfc);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// clear errors
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let errors = r.errorsrc.read().bits();
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r.errorsrc.write(|w| unsafe { w.bits(errors) });
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r.events_rxstarted.reset();
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r.events_txstarted.reset();
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r.events_error.reset();
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r.events_endrx.reset();
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r.events_endtx.reset();
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// Enable interrupts
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r.intenclr.write(|w| unsafe { w.bits(!0) });
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r.intenset.write(|w| {
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w.endtx().set();
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w.rxstarted().set();
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w.error().set();
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w.endrx().set();
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w
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});
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// Enable UARTE instance
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apply_workaround_for_enable_anomaly(&r);
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r.enable.write(|w| w.enable().enabled());
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// Configure byte counter.
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let timer = Timer::new_counter(timer);
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timer.cc(1).write(rx_buffer.len() as u32 * 2);
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timer.cc(1).short_compare_clear();
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timer.clear();
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timer.start();
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let mut ppi_ch1 = Ppi::new_one_to_one(ppi_ch1, Event::from_reg(&r.events_rxdrdy), timer.task_count());
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ppi_ch1.enable();
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s.rx_ppi_ch.store(ppi_ch2.number() as u8, Ordering::Relaxed);
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let mut ppi_group = PpiGroup::new(ppi_group);
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let mut ppi_ch2 = Ppi::new_one_to_two(
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ppi_ch2,
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Event::from_reg(&r.events_endrx),
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Task::from_reg(&r.tasks_startrx),
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ppi_group.task_disable_all(),
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);
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ppi_ch2.disable();
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ppi_group.add_channel(&ppi_ch2);
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U::Interrupt::pend();
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unsafe { U::Interrupt::enable() };
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Self {
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_peri: peri,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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_ppi_group: ppi_group,
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}
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}
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fn pend_irq() {
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U::Interrupt::pend()
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}
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/// Adjust the baud rate to the provided value.
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pub fn set_baudrate(&mut self, baudrate: Baudrate) {
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let r = U::regs();
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r.baudrate.write(|w| w.baudrate().variant(baudrate));
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}
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/// Split the UART in reader and writer parts.
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///
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/// This allows reading and writing concurrently from independent tasks.
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pub fn split<'u>(&'u mut self) -> (BufferedUarteRx<'u, 'd, U, T>, BufferedUarteTx<'u, 'd, U, T>) {
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(BufferedUarteRx { inner: self }, BufferedUarteTx { inner: self })
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}
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async fn inner_read(&self, buf: &mut [u8]) -> Result<usize, Error> {
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let data = self.inner_fill_buf().await?;
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let n = data.len().min(buf.len());
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buf[..n].copy_from_slice(&data[..n]);
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self.inner_consume(n);
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Ok(n)
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}
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async fn inner_write<'a>(&'a self, buf: &'a [u8]) -> Result<usize, Error> {
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poll_fn(move |cx| {
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//trace!("poll_write: {:?}", buf.len());
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let s = U::buffered_state();
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let mut tx = unsafe { s.tx_buf.writer() };
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let tx_buf = tx.push_slice();
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if tx_buf.is_empty() {
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//trace!("poll_write: pending");
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s.tx_waker.register(cx.waker());
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return Poll::Pending;
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}
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let n = min(tx_buf.len(), buf.len());
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tx_buf[..n].copy_from_slice(&buf[..n]);
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tx.push_done(n);
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//trace!("poll_write: queued {:?}", n);
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compiler_fence(Ordering::SeqCst);
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Self::pend_irq();
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Poll::Ready(Ok(n))
|
|
})
|
|
.await
|
|
}
|
|
|
|
async fn inner_flush<'a>(&'a self) -> Result<(), Error> {
|
|
poll_fn(move |cx| {
|
|
//trace!("poll_flush");
|
|
let s = U::buffered_state();
|
|
if !s.tx_buf.is_empty() {
|
|
//trace!("poll_flush: pending");
|
|
s.tx_waker.register(cx.waker());
|
|
return Poll::Pending;
|
|
}
|
|
|
|
Poll::Ready(Ok(()))
|
|
})
|
|
.await
|
|
}
|
|
|
|
async fn inner_fill_buf<'a>(&'a self) -> Result<&'a [u8], Error> {
|
|
poll_fn(move |cx| {
|
|
compiler_fence(Ordering::SeqCst);
|
|
//trace!("poll_read");
|
|
|
|
let r = U::regs();
|
|
let s = U::buffered_state();
|
|
|
|
// Read the RXDRDY counter.
|
|
T::regs().tasks_capture[0].write(|w| unsafe { w.bits(1) });
|
|
let mut end = T::regs().cc[0].read().bits() as usize;
|
|
//trace!(" rxdrdy count = {:?}", end);
|
|
|
|
// We've set a compare channel that resets the counter to 0 when it reaches `len*2`.
|
|
// However, it's unclear if that's instant, or there's a small window where you can
|
|
// still read `len()*2`.
|
|
// This could happen if in one clock cycle the counter is updated, and in the next the
|
|
// clear takes effect. The docs are very sparse, they just say "Task delays: After TIMER
|
|
// is started, the CLEAR, COUNT, and STOP tasks are guaranteed to take effect within one
|
|
// clock cycle of the PCLK16M." :shrug:
|
|
// So, we wrap the counter ourselves, just in case.
|
|
if end > s.rx_buf.len() * 2 {
|
|
end = 0
|
|
}
|
|
|
|
// This logic mirrors `atomic_ring_buffer::Reader::pop_buf()`
|
|
let mut start = s.rx_buf.start.load(Ordering::Relaxed);
|
|
let len = s.rx_buf.len();
|
|
if start == end {
|
|
//trace!(" empty");
|
|
s.rx_waker.register(cx.waker());
|
|
r.intenset.write(|w| w.rxdrdy().set_bit());
|
|
return Poll::Pending;
|
|
}
|
|
|
|
if start >= len {
|
|
start -= len
|
|
}
|
|
if end >= len {
|
|
end -= len
|
|
}
|
|
|
|
let n = if end > start { end - start } else { len - start };
|
|
assert!(n != 0);
|
|
//trace!(" uarte ringbuf: pop_buf {:?}..{:?}", start, start + n);
|
|
|
|
let buf = s.rx_buf.buf.load(Ordering::Relaxed);
|
|
Poll::Ready(Ok(unsafe { slice::from_raw_parts(buf.add(start), n) }))
|
|
})
|
|
.await
|
|
}
|
|
|
|
fn inner_consume(&self, amt: usize) {
|
|
if amt == 0 {
|
|
return;
|
|
}
|
|
|
|
let s = U::buffered_state();
|
|
let mut rx = unsafe { s.rx_buf.reader() };
|
|
rx.pop_done(amt);
|
|
U::regs().intenset.write(|w| w.rxstarted().set());
|
|
}
|
|
|
|
/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
|
|
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
|
|
self.inner_read(buf).await
|
|
}
|
|
|
|
/// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
|
|
pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
|
|
self.inner_fill_buf().await
|
|
}
|
|
|
|
/// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
|
|
pub fn consume(&mut self, amt: usize) {
|
|
self.inner_consume(amt)
|
|
}
|
|
|
|
/// Write a buffer into this writer, returning how many bytes were written.
|
|
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
|
|
self.inner_write(buf).await
|
|
}
|
|
|
|
/// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
|
|
pub async fn flush(&mut self) -> Result<(), Error> {
|
|
self.inner_flush().await
|
|
}
|
|
}
|
|
|
|
/// Reader part of the buffered UARTE driver.
|
|
pub struct BufferedUarteTx<'u, 'd, U: UarteInstance, T: TimerInstance> {
|
|
inner: &'u BufferedUarte<'d, U, T>,
|
|
}
|
|
|
|
impl<'u, 'd, U: UarteInstance, T: TimerInstance> BufferedUarteTx<'u, 'd, U, T> {
|
|
/// Write a buffer into this writer, returning how many bytes were written.
|
|
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
|
|
self.inner.inner_write(buf).await
|
|
}
|
|
|
|
/// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
|
|
pub async fn flush(&mut self) -> Result<(), Error> {
|
|
self.inner.inner_flush().await
|
|
}
|
|
}
|
|
|
|
/// Writer part of the buffered UARTE driver.
|
|
pub struct BufferedUarteRx<'u, 'd, U: UarteInstance, T: TimerInstance> {
|
|
inner: &'u BufferedUarte<'d, U, T>,
|
|
}
|
|
|
|
impl<'u, 'd, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'u, 'd, U, T> {
|
|
/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
|
|
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
|
|
self.inner.inner_read(buf).await
|
|
}
|
|
|
|
/// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
|
|
pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
|
|
self.inner.inner_fill_buf().await
|
|
}
|
|
|
|
/// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
|
|
pub fn consume(&mut self, amt: usize) {
|
|
self.inner.inner_consume(amt)
|
|
}
|
|
}
|
|
|
|
mod _embedded_io {
|
|
use super::*;
|
|
|
|
impl embedded_io_async::Error for Error {
|
|
fn kind(&self) -> embedded_io_async::ErrorKind {
|
|
match *self {}
|
|
}
|
|
}
|
|
|
|
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarte<'d, U, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'u, 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteRx<'u, 'd, U, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'u, 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteTx<'u, 'd, U, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarte<'d, U, T> {
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
self.inner_read(buf).await
|
|
}
|
|
}
|
|
|
|
impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarteRx<'u, 'd, U, T> {
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
self.inner.inner_read(buf).await
|
|
}
|
|
}
|
|
|
|
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarte<'d, U, T> {
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
|
self.inner_fill_buf().await
|
|
}
|
|
|
|
fn consume(&mut self, amt: usize) {
|
|
self.inner_consume(amt)
|
|
}
|
|
}
|
|
|
|
impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarteRx<'u, 'd, U, T> {
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
|
self.inner.inner_fill_buf().await
|
|
}
|
|
|
|
fn consume(&mut self, amt: usize) {
|
|
self.inner.inner_consume(amt)
|
|
}
|
|
}
|
|
|
|
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarte<'d, U, T> {
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
self.inner_write(buf).await
|
|
}
|
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
|
self.inner_flush().await
|
|
}
|
|
}
|
|
|
|
impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarteTx<'u, 'd, U, T> {
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
self.inner.inner_write(buf).await
|
|
}
|
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
|
self.inner.inner_flush().await
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'a, U: UarteInstance, T: TimerInstance> Drop for BufferedUarte<'a, U, T> {
|
|
fn drop(&mut self) {
|
|
self._ppi_group.disable_all();
|
|
|
|
let r = U::regs();
|
|
|
|
self.timer.stop();
|
|
|
|
r.inten.reset();
|
|
r.events_rxto.reset();
|
|
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
|
|
r.events_txstopped.reset();
|
|
r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
|
|
|
|
while r.events_txstopped.read().bits() == 0 {}
|
|
while r.events_rxto.read().bits() == 0 {}
|
|
|
|
r.enable.write(|w| w.enable().disabled());
|
|
|
|
gpio::deconfigure_pin(r.psel.rxd.read().bits());
|
|
gpio::deconfigure_pin(r.psel.txd.read().bits());
|
|
gpio::deconfigure_pin(r.psel.rts.read().bits());
|
|
gpio::deconfigure_pin(r.psel.cts.read().bits());
|
|
|
|
let s = U::buffered_state();
|
|
unsafe {
|
|
s.rx_buf.deinit();
|
|
s.tx_buf.deinit();
|
|
}
|
|
}
|
|
}
|