c6e16c9e4e
Change the UART RX FIFO depth from 1/8 to 7/8. This should allow for buffered receipt of uart data with a lower IRQ load. The PL011 fifo is pretty smart about the fifo, it has an automatic timeout (which triggers an interrupt) of about 4 characters worth of time, so setting this threshold doesn't affect the behavior of receipt of a partially filled fifo. This should not have any affect on the DMA mode, as the DMA will generally drain the fifo as data becomes available. The constraint for the fifo threshold should be determined by expected interrupt latency. The IRQ needs to be able to drain the fifo before it fills. As such, the proper threshold depends on system design and data rate. At full speed (7.8 Mbaud), the remaining 8 characters will come in in about 10us, which is probably insufficient. But, the time is quite adequate at lower speeds.
Embassy RP HAL
HALs implement safe, idiomatic Rust APIs to use the hardware capabilities, so raw register manipulation is not needed.
The embassy-rp HAL targets the Raspberry Pi RP2040 microcontroller. The HAL implements both blocking and async APIs for many peripherals. The benefit of using the async APIs is that the HAL takes care of waiting for peripherals to complete operations in low power mode and handling interrupts, so that applications can focus on more important matters.
embassy-time time driver
If the time-driver feature is enabled, the HAL uses the TIMER peripheral as a global time driver for embassy-time, with a tick rate of 1MHz.
Embedded-hal
The embassy-rp HAL implements the traits from embedded-hal (v0.2 and 1.0) and embedded-hal-async, as well as embedded-io and embedded-io-async.
Interoperability
This crate can run on any executor.
Optionally, some features requiring embassy-time can be activated with the time-driver feature. If you enable it,
you must link an embassy-time driver in your project.