721 lines
23 KiB
Rust
721 lines
23 KiB
Rust
#![no_std]
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#![doc = include_str!("../README.md")]
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#![warn(missing_docs)]
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// must go first.
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mod fmt;
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#[macro_use]
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mod macros;
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mod bank0;
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mod bank1;
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mod bank2;
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mod bank3;
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mod common;
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mod header;
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mod phy;
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mod traits;
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use core::cmp;
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use core::convert::TryInto;
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use embassy_net_driver::{Capabilities, HardwareAddress, LinkState};
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use embassy_time::Duration;
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use embedded_hal::digital::OutputPin;
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use embedded_hal::spi::{Operation, SpiDevice};
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use traits::U16Ext;
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// Total buffer size (see section 3.2)
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const BUF_SZ: u16 = 8 * 1024;
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// Maximum frame length
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const MAX_FRAME_LENGTH: u16 = 1518; // value recommended in the data sheet
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// Size of the Frame check sequence (32-bit CRC)
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const CRC_SZ: u16 = 4;
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// define the boundaries of the TX and RX buffers
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// to workaround errata #5 we do the opposite of what section 6.1 of the data sheet
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// says: we place the RX buffer at address 0 and the TX buffer after it
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const RXST: u16 = 0x0000;
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const RXND: u16 = 0x19ff;
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const TXST: u16 = 0x1a00;
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const _TXND: u16 = 0x1fff;
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const MTU: usize = 1514; // 1500 IP + 14 ethernet header
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/// ENC28J60 embassy-net driver
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pub struct Enc28j60<S, O> {
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mac_addr: [u8; 6],
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spi: S,
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rst: Option<O>,
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bank: Bank,
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// address of the next packet in buffer memory
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next_packet: u16,
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}
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impl<S, O> Enc28j60<S, O>
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where
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S: SpiDevice,
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O: OutputPin,
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{
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/// Create a new ENC28J60 driver instance.
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///
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/// The RST pin is optional. If None, reset will be done with a SPI
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/// soft reset command, instead of via the RST pin.
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pub fn new(spi: S, rst: Option<O>, mac_addr: [u8; 6]) -> Self {
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let mut res = Self {
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mac_addr,
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spi,
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rst,
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bank: Bank::Bank0,
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next_packet: RXST,
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};
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res.init();
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res
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}
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fn init(&mut self) {
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if let Some(rst) = &mut self.rst {
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rst.set_low().unwrap();
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embassy_time::block_for(Duration::from_millis(5));
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rst.set_high().unwrap();
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embassy_time::block_for(Duration::from_millis(5));
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} else {
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embassy_time::block_for(Duration::from_millis(5));
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self.soft_reset();
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embassy_time::block_for(Duration::from_millis(5));
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}
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debug!(
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"enc28j60: erevid {=u8:x}",
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self.read_control_register(bank3::Register::EREVID)
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);
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debug!("enc28j60: waiting for clk");
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while common::ESTAT(self.read_control_register(common::Register::ESTAT)).clkrdy() == 0 {}
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debug!("enc28j60: clk ok");
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if self.read_control_register(bank3::Register::EREVID) == 0 {
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panic!("ErevidIsZero");
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}
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// disable CLKOUT output
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self.write_control_register(bank3::Register::ECOCON, 0);
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self.init_rx();
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// TX start
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// "It is recommended that an even address be used for ETXST"
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debug_assert_eq!(TXST % 2, 0);
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self.write_control_register(bank0::Register::ETXSTL, TXST.low());
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self.write_control_register(bank0::Register::ETXSTH, TXST.high());
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// TX end is set in `transmit`
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// MAC initialization (see section 6.5)
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// 1. Set the MARXEN bit in MACON1 to enable the MAC to receive frames.
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self.write_control_register(
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bank2::Register::MACON1,
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bank2::MACON1::default().marxen(1).passall(0).rxpaus(1).txpaus(1).bits(),
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);
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// 2. Configure the PADCFG, TXCRCEN and FULDPX bits of MACON3.
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self.write_control_register(
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bank2::Register::MACON3,
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bank2::MACON3::default().frmlnen(1).txcrcen(1).padcfg(0b001).bits(),
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);
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// 4. Program the MAMXFL registers with the maximum frame length to be permitted to be
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// received or transmitted
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self.write_control_register(bank2::Register::MAMXFLL, MAX_FRAME_LENGTH.low());
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self.write_control_register(bank2::Register::MAMXFLH, MAX_FRAME_LENGTH.high());
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// 5. Configure the Back-to-Back Inter-Packet Gap register, MABBIPG.
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// Use recommended value of 0x12
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self.write_control_register(bank2::Register::MABBIPG, 0x12);
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// 6. Configure the Non-Back-to-Back Inter-Packet Gap register low byte, MAIPGL.
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// Use recommended value of 0x12
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self.write_control_register(bank2::Register::MAIPGL, 0x12);
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self.write_control_register(bank2::Register::MAIPGH, 0x0c);
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// 9. Program the local MAC address into the MAADR1:MAADR6 registers
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self.write_control_register(bank3::Register::MAADR1, self.mac_addr[0]);
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self.write_control_register(bank3::Register::MAADR2, self.mac_addr[1]);
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self.write_control_register(bank3::Register::MAADR3, self.mac_addr[2]);
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self.write_control_register(bank3::Register::MAADR4, self.mac_addr[3]);
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self.write_control_register(bank3::Register::MAADR5, self.mac_addr[4]);
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self.write_control_register(bank3::Register::MAADR6, self.mac_addr[5]);
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// Set the PHCON2.HDLDIS bit to prevent automatic loopback of the data which is transmitted
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self.write_phy_register(phy::Register::PHCON2, phy::PHCON2::default().hdldis(1).bits());
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// Globally enable interrupts
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//self.bit_field_set(common::Register::EIE, common::EIE::mask().intie());
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// Set the per packet control byte; we'll always use the value 0
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self.write_buffer_memory(Some(TXST), &mut [0]);
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// Enable reception
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self.bit_field_set(common::Register::ECON1, common::ECON1::mask().rxen());
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}
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fn init_rx(&mut self) {
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// RX start
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// "It is recommended that the ERXST Pointer be programmed with an even address"
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self.write_control_register(bank0::Register::ERXSTL, RXST.low());
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self.write_control_register(bank0::Register::ERXSTH, RXST.high());
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// RX read pointer
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// NOTE Errata #14 so we are using an *odd* address here instead of ERXST
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self.write_control_register(bank0::Register::ERXRDPTL, RXND.low());
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self.write_control_register(bank0::Register::ERXRDPTH, RXND.high());
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// RX end
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self.write_control_register(bank0::Register::ERXNDL, RXND.low());
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self.write_control_register(bank0::Register::ERXNDH, RXND.high());
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// decrease the packet count to 0
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while self.read_control_register(bank1::Register::EPKTCNT) != 0 {
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self.bit_field_set(common::Register::ECON2, common::ECON2::mask().pktdec());
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}
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self.next_packet = RXST;
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}
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fn reset_rx(&mut self) {
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self.bit_field_set(common::Register::ECON1, common::ECON1::mask().rxrst());
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self.bit_field_clear(common::Register::ECON1, common::ECON1::mask().rxrst());
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self.init_rx();
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self.bit_field_set(common::Register::ECON1, common::ECON1::mask().rxen());
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}
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/// Returns the device's MAC address
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pub fn address(&self) -> [u8; 6] {
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self.mac_addr
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}
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/// Flushes the transmit buffer, ensuring all pending transmissions have completed
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/// NOTE: The returned packet *must* be `read` or `ignore`-d, otherwise this method will always
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/// return `None` on subsequent invocations
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pub fn receive(&mut self, buf: &mut [u8]) -> Option<usize> {
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if self.pending_packets() == 0 {
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// Errata #6: we can't rely on PKTIF so we check PKTCNT
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return None;
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}
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let curr_packet = self.next_packet;
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// read out the first 6 bytes
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let mut temp_buf = [0; 6];
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self.read_buffer_memory(Some(curr_packet), &mut temp_buf);
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// next packet pointer
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let next_packet = u16::from_parts(temp_buf[0], temp_buf[1]);
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// status vector
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let status = header::RxStatus(u32::from_le_bytes(temp_buf[2..].try_into().unwrap()));
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let len_with_crc = status.byte_count() as u16;
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if len_with_crc < CRC_SZ || len_with_crc > 1600 || next_packet > RXND {
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warn!("RX buffer corrupted, resetting RX logic to recover...");
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self.reset_rx();
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return None;
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}
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let len = len_with_crc - CRC_SZ;
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self.read_buffer_memory(None, &mut buf[..len as usize]);
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// update ERXRDPT
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// due to Errata #14 we must write an odd address to ERXRDPT
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// we know that ERXST = 0, that ERXND is odd and that next_packet is even
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let rxrdpt = if self.next_packet < 1 || self.next_packet > RXND + 1 {
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RXND
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} else {
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self.next_packet - 1
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};
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// "To move ERXRDPT, the host controller must write to ERXRDPTL first."
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self.write_control_register(bank0::Register::ERXRDPTL, rxrdpt.low());
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self.write_control_register(bank0::Register::ERXRDPTH, rxrdpt.high());
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// decrease the packet count
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self.bit_field_set(common::Register::ECON2, common::ECON2::mask().pktdec());
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self.next_packet = next_packet;
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Some(len as usize)
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}
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fn wait_tx_ready(&mut self) {
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for _ in 0u32..10000 {
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if common::ECON1(self.read_control_register(common::Register::ECON1)).txrts() == 0 {
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return;
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}
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}
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// work around errata #12 by resetting the transmit logic before every new
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// transmission
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self.bit_field_set(common::Register::ECON1, common::ECON1::mask().txrst());
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self.bit_field_clear(common::Register::ECON1, common::ECON1::mask().txrst());
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//self.bit_field_clear(common::Register::EIR, {
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// let mask = common::EIR::mask();
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// mask.txerif() | mask.txif()
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//});
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}
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/// Starts the transmission of `bytes`
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///
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/// It's up to the caller to ensure that `bytes` is a valid Ethernet frame. The interface will
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/// take care of appending a (4 byte) CRC to the frame and of padding the frame to the minimum
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/// size allowed by the Ethernet specification (64 bytes, or 46 bytes of payload).
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///
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/// NOTE This method will flush any previous transmission that's in progress
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///
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/// # Panics
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///
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/// If `bytes` length is greater than 1514, the maximum frame length allowed by the interface,
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/// or greater than the transmit buffer
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pub fn transmit(&mut self, bytes: &[u8]) {
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assert!(bytes.len() <= self.mtu() as usize);
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self.wait_tx_ready();
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// NOTE the plus one is to not overwrite the per packet control byte
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let wrpt = TXST + 1;
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// 1. ETXST was set during initialization
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// 2. write the frame to the IC memory
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self.write_buffer_memory(Some(wrpt), bytes);
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let txnd = wrpt + bytes.len() as u16 - 1;
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// 3. Set the end address of the transmit buffer
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self.write_control_register(bank0::Register::ETXNDL, txnd.low());
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self.write_control_register(bank0::Register::ETXNDH, txnd.high());
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// 4. reset interrupt flag
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//self.bit_field_clear(common::Register::EIR, common::EIR::mask().txif());
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// 5. start transmission
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self.bit_field_set(common::Register::ECON1, common::ECON1::mask().txrts());
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// Wait until transmission finishes
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//while common::ECON1(self.read_control_register(common::Register::ECON1)).txrts() == 1 {}
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/*
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// read the transmit status vector
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let mut tx_stat = [0; 7];
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self.read_buffer_memory(None, &mut tx_stat);
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let stat = common::ESTAT(self.read_control_register(common::Register::ESTAT));
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if stat.txabrt() == 1 {
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// work around errata #12 by reading the transmit status vector
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if stat.latecol() == 1 || (tx_stat[2] & (1 << 5)) != 0 {
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panic!("LateCollision")
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} else {
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panic!("TransmitAbort")
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}
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}*/
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}
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/// Get whether the link is up
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pub fn is_link_up(&mut self) -> bool {
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let bits = self.read_phy_register(phy::Register::PHSTAT2);
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phy::PHSTAT2(bits).lstat() == 1
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}
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/// Returns the interface Maximum Transmission Unit (MTU)
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///
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/// The value returned by this function will never exceed 1514 bytes. The actual value depends
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/// on the memory assigned to the transmission buffer when initializing the device
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pub fn mtu(&self) -> u16 {
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cmp::min(BUF_SZ - RXND - 1, MAX_FRAME_LENGTH - CRC_SZ)
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}
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/* Miscellaneous */
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/// Returns the number of packets that have been received but have not been processed yet
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pub fn pending_packets(&mut self) -> u8 {
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self.read_control_register(bank1::Register::EPKTCNT)
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}
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/// Adjusts the receive filter to *accept* these packet types
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pub fn accept(&mut self, packets: &[Packet]) {
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let mask = bank1::ERXFCON::mask();
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let mut val = 0;
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for packet in packets {
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match packet {
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Packet::Broadcast => val |= mask.bcen(),
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Packet::Multicast => val |= mask.mcen(),
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Packet::Unicast => val |= mask.ucen(),
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}
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}
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self.bit_field_set(bank1::Register::ERXFCON, val)
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}
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/// Adjusts the receive filter to *ignore* these packet types
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pub fn ignore(&mut self, packets: &[Packet]) {
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let mask = bank1::ERXFCON::mask();
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let mut val = 0;
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for packet in packets {
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match packet {
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Packet::Broadcast => val |= mask.bcen(),
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Packet::Multicast => val |= mask.mcen(),
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Packet::Unicast => val |= mask.ucen(),
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}
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}
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self.bit_field_clear(bank1::Register::ERXFCON, val)
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}
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/* Private */
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/* Read */
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fn read_control_register<R>(&mut self, register: R) -> u8
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where
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R: Into<Register>,
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{
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self._read_control_register(register.into())
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}
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fn _read_control_register(&mut self, register: Register) -> u8 {
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self.change_bank(register);
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if register.is_eth_register() {
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let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0];
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self.spi.transfer_in_place(&mut buffer).unwrap();
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buffer[1]
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} else {
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// MAC, MII regs need a dummy byte.
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let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0, 0];
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self.spi.transfer_in_place(&mut buffer).unwrap();
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buffer[2]
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}
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}
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fn read_phy_register(&mut self, register: phy::Register) -> u16 {
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// set PHY register address
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self.write_control_register(bank2::Register::MIREGADR, register.addr());
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// start read operation
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self.write_control_register(bank2::Register::MICMD, bank2::MICMD::default().miird(1).bits());
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// wait until the read operation finishes
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while self.read_control_register(bank3::Register::MISTAT) & 0b1 != 0 {}
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self.write_control_register(bank2::Register::MICMD, bank2::MICMD::default().miird(0).bits());
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let l = self.read_control_register(bank2::Register::MIRDL);
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let h = self.read_control_register(bank2::Register::MIRDH);
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(l as u16) | (h as u16) << 8
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}
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/* Write */
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fn _write_control_register(&mut self, register: Register, value: u8) {
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self.change_bank(register);
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let buffer = [Instruction::WCR.opcode() | register.addr(), value];
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self.spi.write(&buffer).unwrap();
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}
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fn write_control_register<R>(&mut self, register: R, value: u8)
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where
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R: Into<Register>,
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{
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self._write_control_register(register.into(), value)
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}
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fn write_phy_register(&mut self, register: phy::Register, value: u16) {
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// set PHY register address
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self.write_control_register(bank2::Register::MIREGADR, register.addr());
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self.write_control_register(bank2::Register::MIWRL, (value & 0xff) as u8);
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// this starts the write operation
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self.write_control_register(bank2::Register::MIWRH, (value >> 8) as u8);
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// wait until the write operation finishes
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while self.read_control_register(bank3::Register::MISTAT) & 0b1 != 0 {}
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}
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/* RMW */
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fn modify_control_register<R, F>(&mut self, register: R, f: F)
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where
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F: FnOnce(u8) -> u8,
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R: Into<Register>,
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{
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self._modify_control_register(register.into(), f)
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}
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fn _modify_control_register<F>(&mut self, register: Register, f: F)
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where
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F: FnOnce(u8) -> u8,
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{
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let r = self._read_control_register(register);
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self._write_control_register(register, f(r))
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}
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/* Auxiliary */
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fn change_bank(&mut self, register: Register) {
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let bank = register.bank();
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if let Some(bank) = bank {
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if self.bank == bank {
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// already on the register bank
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return;
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}
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// change bank
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self.bank = bank;
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match bank {
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Bank::Bank0 => self.bit_field_clear(common::Register::ECON1, 0b11),
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Bank::Bank1 => self.modify_control_register(common::Register::ECON1, |r| (r & !0b11) | 0b01),
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Bank::Bank2 => self.modify_control_register(common::Register::ECON1, |r| (r & !0b11) | 0b10),
|
|
Bank::Bank3 => self.bit_field_set(common::Register::ECON1, 0b11),
|
|
}
|
|
} else {
|
|
// common register
|
|
}
|
|
}
|
|
|
|
/* Primitive operations */
|
|
fn bit_field_clear<R>(&mut self, register: R, mask: u8)
|
|
where
|
|
R: Into<Register>,
|
|
{
|
|
self._bit_field_clear(register.into(), mask)
|
|
}
|
|
|
|
fn _bit_field_clear(&mut self, register: Register, mask: u8) {
|
|
debug_assert!(register.is_eth_register());
|
|
|
|
self.change_bank(register);
|
|
|
|
self.spi
|
|
.write(&[Instruction::BFC.opcode() | register.addr(), mask])
|
|
.unwrap();
|
|
}
|
|
|
|
fn bit_field_set<R>(&mut self, register: R, mask: u8)
|
|
where
|
|
R: Into<Register>,
|
|
{
|
|
self._bit_field_set(register.into(), mask)
|
|
}
|
|
|
|
fn _bit_field_set(&mut self, register: Register, mask: u8) {
|
|
debug_assert!(register.is_eth_register());
|
|
|
|
self.change_bank(register);
|
|
|
|
self.spi
|
|
.write(&[Instruction::BFS.opcode() | register.addr(), mask])
|
|
.unwrap();
|
|
}
|
|
|
|
fn read_buffer_memory(&mut self, addr: Option<u16>, buf: &mut [u8]) {
|
|
if let Some(addr) = addr {
|
|
self.write_control_register(bank0::Register::ERDPTL, addr.low());
|
|
self.write_control_register(bank0::Register::ERDPTH, addr.high());
|
|
}
|
|
|
|
self.spi
|
|
.transaction(&mut [Operation::Write(&[Instruction::RBM.opcode()]), Operation::Read(buf)])
|
|
.unwrap();
|
|
}
|
|
|
|
fn soft_reset(&mut self) {
|
|
self.spi.write(&[Instruction::SRC.opcode()]).unwrap();
|
|
}
|
|
|
|
fn write_buffer_memory(&mut self, addr: Option<u16>, buffer: &[u8]) {
|
|
if let Some(addr) = addr {
|
|
self.write_control_register(bank0::Register::EWRPTL, addr.low());
|
|
self.write_control_register(bank0::Register::EWRPTH, addr.high());
|
|
}
|
|
|
|
self.spi
|
|
.transaction(&mut [Operation::Write(&[Instruction::WBM.opcode()]), Operation::Write(buffer)])
|
|
.unwrap();
|
|
}
|
|
}
|
|
|
|
#[derive(Clone, Copy, PartialEq)]
|
|
enum Bank {
|
|
Bank0,
|
|
Bank1,
|
|
Bank2,
|
|
Bank3,
|
|
}
|
|
|
|
#[derive(Clone, Copy)]
|
|
enum Instruction {
|
|
/// Read Control Register
|
|
RCR = 0b000_00000,
|
|
/// Read Buffer Memory
|
|
RBM = 0b001_11010,
|
|
/// Write Control Register
|
|
WCR = 0b010_00000,
|
|
/// Write Buffer Memory
|
|
WBM = 0b011_11010,
|
|
/// Bit Field Set
|
|
BFS = 0b100_00000,
|
|
/// Bit Field Clear
|
|
BFC = 0b101_00000,
|
|
/// System Reset Command
|
|
SRC = 0b111_11111,
|
|
}
|
|
|
|
impl Instruction {
|
|
fn opcode(&self) -> u8 {
|
|
*self as u8
|
|
}
|
|
}
|
|
|
|
#[derive(Clone, Copy)]
|
|
enum Register {
|
|
Bank0(bank0::Register),
|
|
Bank1(bank1::Register),
|
|
Bank2(bank2::Register),
|
|
Bank3(bank3::Register),
|
|
Common(common::Register),
|
|
}
|
|
|
|
impl Register {
|
|
fn addr(&self) -> u8 {
|
|
match *self {
|
|
Register::Bank0(r) => r.addr(),
|
|
Register::Bank1(r) => r.addr(),
|
|
Register::Bank2(r) => r.addr(),
|
|
Register::Bank3(r) => r.addr(),
|
|
Register::Common(r) => r.addr(),
|
|
}
|
|
}
|
|
|
|
fn bank(&self) -> Option<Bank> {
|
|
Some(match *self {
|
|
Register::Bank0(_) => Bank::Bank0,
|
|
Register::Bank1(_) => Bank::Bank1,
|
|
Register::Bank2(_) => Bank::Bank2,
|
|
Register::Bank3(_) => Bank::Bank3,
|
|
Register::Common(_) => return None,
|
|
})
|
|
}
|
|
|
|
fn is_eth_register(&self) -> bool {
|
|
match *self {
|
|
Register::Bank0(r) => r.is_eth_register(),
|
|
Register::Bank1(r) => r.is_eth_register(),
|
|
Register::Bank2(r) => r.is_eth_register(),
|
|
Register::Bank3(r) => r.is_eth_register(),
|
|
Register::Common(r) => r.is_eth_register(),
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Packet type, used to configure receive filters
|
|
#[non_exhaustive]
|
|
#[derive(Clone, Copy, Eq, PartialEq)]
|
|
pub enum Packet {
|
|
/// Broadcast packets
|
|
Broadcast,
|
|
/// Multicast packets
|
|
Multicast,
|
|
/// Unicast packets
|
|
Unicast,
|
|
}
|
|
|
|
static mut TX_BUF: [u8; MTU] = [0; MTU];
|
|
static mut RX_BUF: [u8; MTU] = [0; MTU];
|
|
|
|
impl<S, O> embassy_net_driver::Driver for Enc28j60<S, O>
|
|
where
|
|
S: SpiDevice,
|
|
O: OutputPin,
|
|
{
|
|
type RxToken<'a> = RxToken<'a>
|
|
where
|
|
Self: 'a;
|
|
|
|
type TxToken<'a> = TxToken<'a, S, O>
|
|
where
|
|
Self: 'a;
|
|
|
|
fn receive(&mut self, cx: &mut core::task::Context) -> Option<(Self::RxToken<'_>, Self::TxToken<'_>)> {
|
|
let rx_buf = unsafe { &mut RX_BUF };
|
|
let tx_buf = unsafe { &mut TX_BUF };
|
|
if let Some(n) = self.receive(rx_buf) {
|
|
Some((RxToken { buf: &mut rx_buf[..n] }, TxToken { buf: tx_buf, eth: self }))
|
|
} else {
|
|
cx.waker().wake_by_ref();
|
|
None
|
|
}
|
|
}
|
|
|
|
fn transmit(&mut self, _cx: &mut core::task::Context) -> Option<Self::TxToken<'_>> {
|
|
let tx_buf = unsafe { &mut TX_BUF };
|
|
Some(TxToken { buf: tx_buf, eth: self })
|
|
}
|
|
|
|
fn link_state(&mut self, cx: &mut core::task::Context) -> LinkState {
|
|
cx.waker().wake_by_ref();
|
|
match self.is_link_up() {
|
|
true => LinkState::Up,
|
|
false => LinkState::Down,
|
|
}
|
|
}
|
|
|
|
fn capabilities(&self) -> Capabilities {
|
|
let mut caps = Capabilities::default();
|
|
caps.max_transmission_unit = MTU;
|
|
caps
|
|
}
|
|
|
|
fn hardware_address(&self) -> HardwareAddress {
|
|
HardwareAddress::Ethernet(self.mac_addr)
|
|
}
|
|
}
|
|
|
|
/// embassy-net RX token.
|
|
pub struct RxToken<'a> {
|
|
buf: &'a mut [u8],
|
|
}
|
|
|
|
impl<'a> embassy_net_driver::RxToken for RxToken<'a> {
|
|
fn consume<R, F>(self, f: F) -> R
|
|
where
|
|
F: FnOnce(&mut [u8]) -> R,
|
|
{
|
|
f(self.buf)
|
|
}
|
|
}
|
|
|
|
/// embassy-net TX token.
|
|
pub struct TxToken<'a, S, O>
|
|
where
|
|
S: SpiDevice,
|
|
O: OutputPin,
|
|
{
|
|
eth: &'a mut Enc28j60<S, O>,
|
|
buf: &'a mut [u8],
|
|
}
|
|
|
|
impl<'a, S, O> embassy_net_driver::TxToken for TxToken<'a, S, O>
|
|
where
|
|
S: SpiDevice,
|
|
O: OutputPin,
|
|
{
|
|
fn consume<R, F>(self, len: usize, f: F) -> R
|
|
where
|
|
F: FnOnce(&mut [u8]) -> R,
|
|
{
|
|
assert!(len <= self.buf.len());
|
|
let r = f(&mut self.buf[..len]);
|
|
self.eth.transmit(&self.buf[..len]);
|
|
r
|
|
}
|
|
}
|