440 lines
13 KiB
Rust
440 lines
13 KiB
Rust
#![macro_use]
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use core::future::Future;
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use core::task::Poll;
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use atomic_polyfill::{AtomicU8, Ordering};
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::util::{AtomicWaker, OnDrop};
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use futures::future::poll_fn;
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use crate::dma_traits::{ReadDma, WriteDma};
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use crate::interrupt;
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use crate::pac;
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use crate::pac::bdma::vals;
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const CH_COUNT: usize = pac::peripheral_count!(DMA) * 8;
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const CH_STATUS_NONE: u8 = 0;
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const CH_STATUS_COMPLETED: u8 = 1;
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const CH_STATUS_ERROR: u8 = 2;
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struct State {
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ch_wakers: [AtomicWaker; CH_COUNT],
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ch_status: [AtomicU8; CH_COUNT],
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}
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impl State {
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const fn new() -> Self {
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const AW: AtomicWaker = AtomicWaker::new();
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const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
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Self {
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ch_wakers: [AW; CH_COUNT],
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ch_status: [AU; CH_COUNT],
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}
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}
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}
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static STATE: State = State::new();
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#[allow(unused)]
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pub(crate) async unsafe fn transfer_p2m(
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regs: pac::bdma::Ch,
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state_number: usize,
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src: *const u8,
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dst: &mut [u8],
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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#[cfg(dmamux)] request: u8,
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) {
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// ndtr is max 16 bits.
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assert!(dst.len() <= 0xFFFF);
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// Reset status
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// Generate a DMB here to flush the store buffer (M7) before enabling the DMA
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STATE.ch_status[state_number].store(CH_STATUS_NONE, Ordering::Release);
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let on_drop = OnDrop::new(|| unsafe {
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regs.cr().modify(|w| {
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w.set_tcie(false);
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w.set_teie(false);
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w.set_en(false);
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});
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while regs.cr().read().en() {}
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});
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#[cfg(dmamux)]
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crate::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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regs.par().write_value(src as u32);
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regs.mar().write_value(dst.as_mut_ptr() as u32);
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regs.ndtr().write(|w| w.set_ndt(dst.len() as u16));
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regs.cr().write(|w| {
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w.set_psize(vals::Size::BITS8);
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w.set_msize(vals::Size::BITS8);
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w.set_minc(vals::Inc::ENABLED);
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w.set_teie(true);
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w.set_tcie(true);
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w.set_en(true);
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});
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let res = poll_fn(|cx| {
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STATE.ch_wakers[state_number].register(cx.waker());
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match STATE.ch_status[state_number].load(Ordering::Acquire) {
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CH_STATUS_NONE => Poll::Pending,
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x => Poll::Ready(x),
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}
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})
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.await;
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// TODO handle error
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assert!(res == CH_STATUS_COMPLETED);
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}
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#[allow(unused)]
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pub(crate) async unsafe fn transfer_m2p(
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regs: pac::bdma::Ch,
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state_number: usize,
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src: &[u8],
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dst: *mut u8,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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#[cfg(dmamux)] request: u8,
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) {
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// ndtr is max 16 bits.
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assert!(src.len() <= 0xFFFF);
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// Reset status
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// Generate a DMB here to flush the store buffer (M7) before enabling the DMA
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STATE.ch_status[state_number].store(CH_STATUS_NONE, Ordering::Release);
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let on_drop = OnDrop::new(|| unsafe {
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regs.cr().modify(|w| {
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w.set_tcie(false);
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w.set_teie(false);
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w.set_en(false);
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});
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while regs.cr().read().en() {}
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});
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#[cfg(dmamux)]
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crate::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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regs.par().write_value(dst as u32);
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regs.mar().write_value(src.as_ptr() as u32);
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regs.ndtr().write(|w| w.set_ndt(src.len() as u16));
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regs.cr().write(|w| {
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w.set_psize(vals::Size::BITS8);
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w.set_msize(vals::Size::BITS8);
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w.set_minc(vals::Inc::ENABLED);
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w.set_dir(vals::Dir::FROMMEMORY);
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w.set_teie(true);
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w.set_tcie(true);
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w.set_en(true);
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});
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let res = poll_fn(|cx| {
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STATE.ch_wakers[state_number].register(cx.waker());
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match STATE.ch_status[state_number].load(Ordering::Acquire) {
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CH_STATUS_NONE => Poll::Pending,
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x => Poll::Ready(x),
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}
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})
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.await;
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// TODO handle error
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assert!(res == CH_STATUS_COMPLETED);
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}
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unsafe fn on_irq() {
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pac::peripherals! {
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(bdma, $dma:ident) => {
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let isr = pac::$dma.isr().read();
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pac::$dma.ifcr().write_value(isr);
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let dman = <crate::peripherals::$dma as sealed::Dma>::num() as usize;
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for chn in 0..7 {
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let n = dman * 8 + chn;
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if isr.teif(chn) {
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STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
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STATE.ch_wakers[n].wake();
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} else if isr.tcif(chn) {
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STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
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STATE.ch_wakers[n].wake();
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}
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}
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};
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}
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}
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use crate::rcc::sealed::RccPeripheral;
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/// safety: must be called only once
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pub(crate) unsafe fn init() {
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pac::interrupts! {
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(DMA, $irq:ident) => {
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crate::interrupt::$irq::steal().enable();
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};
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}
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pac::peripherals! {
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(bdma, $peri:ident) => {
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crate::peripherals::$peri::enable();
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};
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}
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}
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pub(crate) mod sealed {
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use super::*;
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pub trait Dma {
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fn num() -> u8;
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}
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pub trait Channel {
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fn dma_regs() -> pac::bdma::Dma;
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fn state_num(&self) -> usize;
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fn ch_num(&self) -> u8;
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fn regs(&self) -> pac::bdma::Ch {
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Self::dma_regs().ch(self.ch_num() as usize)
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}
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}
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}
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pub trait Dma: sealed::Dma + Sized {}
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pub trait Channel: sealed::Channel + Sized {}
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macro_rules! impl_dma {
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($peri:ident, $num:expr) => {
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impl Dma for crate::peripherals::$peri {}
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impl sealed::Dma for crate::peripherals::$peri {
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fn num() -> u8 {
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$num
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}
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}
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};
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}
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macro_rules! impl_dma_channel {
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($channel_peri:ident, $dma_peri:ident, $dma_num:expr, $ch_num:expr) => {
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impl Channel for crate::peripherals::$channel_peri {}
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impl sealed::Channel for crate::peripherals::$channel_peri {
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#[inline]
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fn dma_regs() -> pac::bdma::Dma {
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crate::pac::$dma_peri
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}
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fn state_num(&self) -> usize {
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($dma_num * 8) + $ch_num
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}
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fn ch_num(&self) -> u8 {
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$ch_num
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}
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}
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#[cfg(not(dmamux))]
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impl<T> WriteDma<T> for crate::peripherals::$channel_peri
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where
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T: 'static,
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{
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type WriteDmaFuture<'a> = impl Future<Output = ()>;
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fn transfer<'a>(&'a mut self, buf: &'a [u8], dst: *mut u8) -> Self::WriteDmaFuture<'a>
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where
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T: 'a,
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{
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use sealed::Channel as _Channel;
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let state_num = self.state_num();
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let regs = self.regs();
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unsafe { transfer_m2p(regs, state_num, buf, dst) }
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}
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}
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#[cfg(dmamux)]
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impl<T> WriteDma<T> for crate::peripherals::$channel_peri
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where
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Self: crate::dmamux::sealed::PeripheralChannel<T, crate::dmamux::M2P>,
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T: 'static,
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{
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type WriteDmaFuture<'a> = impl Future<Output = ()>;
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fn transfer<'a>(&'a mut self, buf: &'a [u8], dst: *mut u8) -> Self::WriteDmaFuture<'a>
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where
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T: 'a,
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{
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use sealed::Channel as _Channel;
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let state_num = self.state_num();
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let regs = self.regs();
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use crate::dmamux::sealed::Channel as _MuxChannel;
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use crate::dmamux::sealed::PeripheralChannel;
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let dmamux_regs = self.dmamux_regs();
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let dmamux_ch_num = self.dmamux_ch_num();
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let request = PeripheralChannel::<T, crate::dmamux::M2P>::request(self);
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unsafe {
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transfer_m2p(
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regs,
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state_num,
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buf,
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dst,
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dmamux_regs,
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dmamux_ch_num,
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request,
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)
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}
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}
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}
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#[cfg(not(dmamux))]
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impl<T> ReadDma<T> for crate::peripherals::$channel_peri
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where
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T: 'static,
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{
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type ReadDmaFuture<'a> = impl Future<Output = ()>;
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fn transfer<'a>(
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&'a mut self,
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src: *const u8,
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buf: &'a mut [u8],
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) -> Self::ReadDmaFuture<'a>
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where
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T: 'a,
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{
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use sealed::Channel as _Channel;
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let state_num = self.state_num();
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let regs = self.regs();
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unsafe { transfer_p2m(regs, state_num, src, buf) }
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}
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}
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#[cfg(dmamux)]
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impl<T> ReadDma<T> for crate::peripherals::$channel_peri
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where
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Self: crate::dmamux::sealed::PeripheralChannel<T, crate::dmamux::M2P>,
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T: 'static,
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{
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type ReadDmaFuture<'a> = impl Future<Output = ()>;
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fn transfer<'a>(
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&'a mut self,
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src: *const u8,
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buf: &'a mut [u8],
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) -> Self::ReadDmaFuture<'a>
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where
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T: 'a,
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{
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use sealed::Channel as _Channel;
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let state_num = self.state_num();
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let regs = self.regs();
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use crate::dmamux::sealed::Channel as _MuxChannel;
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use crate::dmamux::sealed::PeripheralChannel;
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let dmamux_regs = self.dmamux_regs();
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let dmamux_ch_num = self.dmamux_ch_num();
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let request = PeripheralChannel::<T, crate::dmamux::M2P>::request(self);
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unsafe {
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transfer_p2m(
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regs,
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state_num,
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src,
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buf,
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dmamux_regs,
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dmamux_ch_num,
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request,
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)
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}
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}
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}
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};
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}
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pac::peripherals! {
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(bdma, DMA1) => {
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impl_dma!(DMA1, 0);
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pac::bdma_channels! {
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($channel_peri:ident, DMA1, $channel_num:expr) => {
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impl_dma_channel!($channel_peri, DMA1, 0, $channel_num);
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};
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}
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};
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(bdma, DMA2) => {
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impl_dma!(DMA2, 1);
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pac::bdma_channels! {
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($channel_peri:ident, DMA2, $channel_num:expr) => {
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impl_dma_channel!($channel_peri, DMA2, 1, $channel_num);
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};
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}
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};
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// Because H7cm changes the naming
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(bdma, BDMA) => {
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impl_dma!(BDMA, 0);
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pac::bdma_channels! {
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($channel_peri:ident, BDMA, $channel_num:expr) => {
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impl_dma_channel!($channel_peri, BDMA, 0, $channel_num);
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};
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}
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};
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}
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pac::interrupts! {
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(DMA, $irq:ident) => {
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#[crate::interrupt]
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unsafe fn $irq () {
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on_irq()
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}
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};
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}
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#[cfg(usart)]
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use crate::usart;
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#[cfg(not(dmamux))]
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pac::peripheral_dma_channels! {
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($peri:ident, usart, $kind:ident, RX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl usart::RxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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impl usart::sealed::RxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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};
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($peri:ident, usart, $kind:ident, TX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl usart::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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impl usart::sealed::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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};
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($peri:ident, uart, $kind:ident, RX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl usart::RxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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impl usart::sealed::RxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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};
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($peri:ident, uart, $kind:ident, TX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl usart::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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impl usart::sealed::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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};
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}
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#[cfg(dmamux)]
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pac::peripherals! {
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(usart, $peri:ident) => {
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pac::bdma_channels! {
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($channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl usart::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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impl usart::sealed::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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};
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}
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};
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(uart, $peri:ident) => {
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pac::bdma_channels! {
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($channel_peri:ident, $dma_peri:ident, $channel_num:expr) => {
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impl usart::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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impl usart::sealed::TxDma<crate::peripherals::$peri> for crate::peripherals::$channel_peri { }
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};
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}
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};
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}
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