381 lines
12 KiB
Rust
381 lines
12 KiB
Rust
use stm32_metapac::flash::vals::Latency;
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use stm32_metapac::rcc::vals::{Adcsel, Sw};
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use stm32_metapac::FLASH;
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pub use crate::pac::rcc::vals::{
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Adcsel as AdcClockSource, Clk48sel as Clk48Src, Fdcansel as FdCanClockSource, Hpre as AHBPrescaler,
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Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc, Ppre as APBPrescaler,
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Sw as Sysclk,
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};
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use crate::pac::{PWR, RCC};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// HSE Mode
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1)
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Bypass,
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}
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/// HSE Configuration
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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/// PLL Configuration
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///
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/// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
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/// dividers. Be sure to keep check the datasheet for your specific part for the appropriate
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/// frequency ranges for each of these settings.
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pub struct Pll {
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/// PLL Source clock selection.
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pub source: Pllsrc,
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/// PLL pre-divider
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pub prediv: PllPreDiv,
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/// PLL multiplication factor for VCO
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pub mul: PllMul,
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/// PLL division factor for P clock (ADC Clock)
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pub divp: Option<PllPDiv>,
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/// PLL division factor for Q clock (USB, I2S23, SAI1, FDCAN, QSPI)
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pub divq: Option<PllQDiv>,
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/// PLL division factor for R clock (SYSCLK)
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pub divr: Option<PllRDiv>,
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}
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/// Clocks configutation
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#[non_exhaustive]
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pub struct Config {
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/// HSI Enable
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pub hsi: bool,
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/// HSE Configuration
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pub hse: Option<Hse>,
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/// System Clock Configuration
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pub sys: Sysclk,
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/// HSI48 Configuration
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pub hsi48: Option<super::Hsi48Config>,
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/// PLL Configuration
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pub pll: Option<Pll>,
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/// Iff PLL is requested as the main clock source in the `mux` field then the PLL configuration
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/// MUST turn on the PLLR output.
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub low_power_run: bool,
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/// Sets the clock source for the 48MHz clock used by the USB and RNG peripherals.
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pub clk48_src: Clk48Src,
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/// Low-Speed Clock Configuration
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pub ls: super::LsConfig,
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/// Clock Source for ADCs 1 and 2
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pub adc12_clock_source: AdcClockSource,
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/// Clock Source for ADCs 3, 4 and 5
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pub adc345_clock_source: AdcClockSource,
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/// Clock Source for FDCAN
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pub fdcan_clock_source: FdCanClockSource,
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/// Enable range1 boost mode
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/// Recommended when the SYSCLK frequency is greater than 150MHz.
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pub boost: bool,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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hsi: true,
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hse: None,
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sys: Sysclk::HSI,
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hsi48: Some(Default::default()),
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pll: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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low_power_run: false,
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clk48_src: Clk48Src::HSI48,
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ls: Default::default(),
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adc12_clock_source: Adcsel::DISABLE,
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adc345_clock_source: Adcsel::DISABLE,
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fdcan_clock_source: FdCanClockSource::PCLK1,
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boost: false,
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}
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}
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}
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pub struct PllFreq {
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pub pll_p: Option<Hertz>,
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pub pll_q: Option<Hertz>,
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pub pll_r: Option<Hertz>,
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}
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pub(crate) unsafe fn init(config: Config) {
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// Configure HSI
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let hsi = match config.hsi {
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false => {
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RCC.cr().modify(|w| w.set_hsion(false));
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None
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}
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true => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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Some(HSI_FREQ)
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}
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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match hse.mode {
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HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
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HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
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}
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RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// Configure HSI48 if required
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if let Some(hsi48_config) = config.hsi48 {
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super::init_hsi48(hsi48_config);
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}
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let pll_freq = config.pll.map(|pll_config| {
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let src_freq = match pll_config.source {
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Pllsrc::HSI => unwrap!(hsi),
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Pllsrc::HSE => unwrap!(hse),
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_ => unreachable!(),
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};
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// TODO: check PLL input, internal and output frequencies for validity
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// Disable PLL before configuration
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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let internal_freq = src_freq / pll_config.prediv * pll_config.mul;
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RCC.pllcfgr().write(|w| {
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w.set_plln(pll_config.mul);
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w.set_pllm(pll_config.prediv);
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w.set_pllsrc(pll_config.source.into());
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});
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let pll_p_freq = pll_config.divp.map(|div_p| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllp(div_p);
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w.set_pllpen(true);
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});
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internal_freq / div_p
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});
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let pll_q_freq = pll_config.divq.map(|div_q| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllq(div_q);
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w.set_pllqen(true);
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});
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internal_freq / div_q
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});
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let pll_r_freq = pll_config.divr.map(|div_r| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllr(div_r);
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w.set_pllren(true);
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});
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internal_freq / div_r
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});
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// Enable the PLL
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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PllFreq {
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pll_p: pll_p_freq,
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pll_q: pll_q_freq,
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pll_r: pll_r_freq,
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}
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});
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let (sys_clk, sw) = match config.sys {
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Sysclk::HSI => (HSI_FREQ, Sw::HSI),
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Sysclk::HSE => (unwrap!(hse), Sw::HSE),
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Sysclk::PLL1_R => {
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assert!(pll_freq.is_some());
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assert!(pll_freq.as_ref().unwrap().pll_r.is_some());
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let freq = pll_freq.as_ref().unwrap().pll_r.unwrap().0;
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assert!(freq <= 170_000_000);
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(Hertz(freq), Sw::PLL1_R)
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}
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_ => unreachable!(),
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};
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// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
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let ahb_freq = sys_clk / config.ahb_pre;
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// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
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// TODO: according to RM0440 p235, when switching from range1-normal to range1-boost, it’s necessary to divide
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// SYSCLK by 2 using the AHB prescaler, set boost and flash read latency, switch system frequency, wait 1us and
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// reconfigure the AHB prescaler as desired. Unclear whether this is always necessary.
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PWR.cr5().modify(|w| w.set_r1mode(!config.boost));
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// Configure flash read access latency based on boost mode and frequency (RM0440 p98)
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FLASH.acr().modify(|w| {
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w.set_latency(match (config.boost, ahb_freq.0) {
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(true, ..=34_000_000) => Latency::WS0,
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(true, ..=68_000_000) => Latency::WS1,
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(true, ..=102_000_000) => Latency::WS2,
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(true, ..=136_000_000) => Latency::WS3,
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(true, _) => Latency::WS4,
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(false, ..=36_000_000) => Latency::WS0,
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(false, ..=60_000_000) => Latency::WS1,
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(false, ..=90_000_000) => Latency::WS2,
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(false, ..=120_000_000) => Latency::WS3,
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(false, _) => Latency::WS4,
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})
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});
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// Now that boost mode and flash read access latency are configured, set up SYSCLK
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RCC.cfgr().modify(|w| {
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w.set_sw(sw);
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w.set_hpre(config.ahb_pre);
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w.set_ppre1(config.apb1_pre);
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w.set_ppre2(config.apb2_pre);
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});
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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// Configure the 48MHz clock source for USB and RNG peripherals.
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{
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let source = match config.clk48_src {
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Clk48Src::PLL1_Q => {
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// Make sure the PLLQ is enabled and running at 48Mhz
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let pllq_freq = pll_freq.as_ref().and_then(|f| f.pll_q);
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assert!(pllq_freq.is_some() && pllq_freq.unwrap().0 == 48_000_000);
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crate::pac::rcc::vals::Clk48sel::PLL1_Q
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}
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Clk48Src::HSI48 => {
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// Make sure HSI48 is enabled
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assert!(config.hsi48.is_some());
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crate::pac::rcc::vals::Clk48sel::HSI48
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}
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_ => unreachable!(),
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};
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RCC.ccipr().modify(|w| w.set_clk48sel(source));
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}
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RCC.ccipr().modify(|w| w.set_adc12sel(config.adc12_clock_source));
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RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source));
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RCC.ccipr().modify(|w| w.set_fdcansel(config.fdcan_clock_source));
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let adc12_ck = match config.adc12_clock_source {
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AdcClockSource::DISABLE => None,
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AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
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AdcClockSource::SYS => Some(sys_clk),
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_ => unreachable!(),
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};
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let adc345_ck = match config.adc345_clock_source {
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AdcClockSource::DISABLE => None,
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AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
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AdcClockSource::SYS => Some(sys_clk),
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_ => unreachable!(),
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};
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if config.low_power_run {
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assert!(sys_clk <= Hertz(2_000_000));
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PWR.cr1().modify(|w| w.set_lpr(true));
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}
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let rtc = config.ls.init();
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set_clocks!(
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sys: Some(sys_clk),
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hclk1: Some(ahb_freq),
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hclk2: Some(ahb_freq),
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hclk3: Some(ahb_freq),
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pclk1: Some(apb1_freq),
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pclk1_tim: Some(apb1_tim_freq),
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pclk2: Some(apb2_freq),
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pclk2_tim: Some(apb2_tim_freq),
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adc: adc12_ck,
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adc34: adc345_ck,
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pll1_p: pll_freq.as_ref().and_then(|pll| pll.pll_p),
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pll1_q: pll_freq.as_ref().and_then(|pll| pll.pll_p),
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hse: hse,
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rtc: rtc,
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);
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}
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// TODO: if necessary, make more of these gated behind cfg attrs
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mod max {
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use core::ops::RangeInclusive;
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use crate::time::Hertz;
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/// HSE 4-48MHz (RM0440 p280)
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pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(48_000_000);
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/// External Clock ?-48MHz (RM0440 p280)
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pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
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// SYSCLK ?-170MHz (RM0440 p282)
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//pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
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// PLL Output frequency ?-170MHz (RM0440 p281)
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//pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
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// Left over from f.rs, remove if not necessary
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//pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
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//pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
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//pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
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}
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