921780e6bf
- Move typelevel interrupts to a special-purpose mod: `embassy_xx::interrupt::typelevel`. - Reexport the PAC interrupt enum in `embassy_xx::interrupt`. This has a few advantages: - The `embassy_xx::interrupt` module is now more "standard". - It works with `cortex-m` functions for manipulating interrupts, for example. - It works with RTIC. - the interrupt enum allows holding value that can be "any interrupt at runtime", this can't be done with typelevel irqs. - When "const-generics on enums" is stable, we can remove the typelevel interrupts without disruptive changes to `embassy_xx::interrupt`.
898 lines
29 KiB
Rust
898 lines
29 KiB
Rust
//! I2C-compatible Two Wire Interface in master mode (TWIM) driver.
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#![macro_use]
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use core::future::{poll_fn, Future};
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use core::marker::PhantomData;
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use core::sync::atomic::compiler_fence;
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use core::sync::atomic::Ordering::SeqCst;
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use core::task::Poll;
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use embassy_embedded_hal::SetConfig;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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#[cfg(feature = "time")]
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use embassy_time::{Duration, Instant};
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use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
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use crate::gpio::Pin as GpioPin;
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use crate::interrupt::typelevel::Interrupt;
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use crate::util::{slice_in_ram, slice_in_ram_or};
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use crate::{gpio, interrupt, pac, Peripheral};
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/// TWI frequency
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#[derive(Clone, Copy)]
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pub enum Frequency {
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/// 100 kbps
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K100 = 26738688,
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/// 250 kbps
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K250 = 67108864,
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/// 400 kbps
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K400 = 104857600,
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}
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/// TWIM config.
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#[non_exhaustive]
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pub struct Config {
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/// Frequency
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pub frequency: Frequency,
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/// Enable high drive for the SDA line.
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pub sda_high_drive: bool,
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/// Enable internal pullup for the SDA line.
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///
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/// Note that using external pullups is recommended for I2C, and
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/// most boards already have them.
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pub sda_pullup: bool,
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/// Enable high drive for the SCL line.
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pub scl_high_drive: bool,
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/// Enable internal pullup for the SCL line.
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///
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/// Note that using external pullups is recommended for I2C, and
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/// most boards already have them.
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pub scl_pullup: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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frequency: Frequency::K100,
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scl_high_drive: false,
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sda_pullup: false,
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sda_high_drive: false,
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scl_pullup: false,
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}
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}
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}
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/// TWI error.
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// TX buffer was too long.
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TxBufferTooLong,
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/// RX buffer was too long.
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RxBufferTooLong,
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/// Data transmit failed.
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Transmit,
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/// Data reception failed.
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Receive,
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/// The buffer is not in data RAM. It's most likely in flash, and nRF's DMA cannot access flash.
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BufferNotInRAM,
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/// Didn't receive an ACK bit after the address byte. Address might be wrong, or the i2c device chip might not be connected properly.
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AddressNack,
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/// Didn't receive an ACK bit after a data byte.
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DataNack,
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/// Overrun error.
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Overrun,
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/// Timeout error.
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Timeout,
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}
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let r = T::regs();
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let s = T::state();
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if r.events_stopped.read().bits() != 0 {
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s.end_waker.wake();
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r.intenclr.write(|w| w.stopped().clear());
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}
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if r.events_error.read().bits() != 0 {
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s.end_waker.wake();
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r.intenclr.write(|w| w.error().clear());
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}
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}
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}
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/// TWI driver.
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pub struct Twim<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance> Twim<'d, T> {
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/// Create a new TWI driver.
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pub fn new(
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twim: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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sda: impl Peripheral<P = impl GpioPin> + 'd,
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scl: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(twim, sda, scl);
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let r = T::regs();
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// Configure pins
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sda.conf().write(|w| {
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w.dir().input();
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w.input().connect();
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if config.sda_high_drive {
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w.drive().h0d1();
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} else {
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w.drive().s0d1();
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}
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if config.sda_pullup {
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w.pull().pullup();
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}
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w
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});
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scl.conf().write(|w| {
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w.dir().input();
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w.input().connect();
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if config.scl_high_drive {
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w.drive().h0d1();
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} else {
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w.drive().s0d1();
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}
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if config.scl_pullup {
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w.pull().pullup();
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}
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w
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});
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// Select pins.
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r.psel.sda.write(|w| unsafe { w.bits(sda.psel_bits()) });
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r.psel.scl.write(|w| unsafe { w.bits(scl.psel_bits()) });
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// Enable TWIM instance.
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r.enable.write(|w| w.enable().enabled());
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// Configure frequency.
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r.frequency
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.write(|w| unsafe { w.frequency().bits(config.frequency as u32) });
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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Self { _p: twim }
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}
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/// Set TX buffer, checking that it is in RAM and has suitable length.
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unsafe fn set_tx_buffer(&mut self, buffer: &[u8]) -> Result<(), Error> {
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slice_in_ram_or(buffer, Error::BufferNotInRAM)?;
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::TxBufferTooLong);
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}
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let r = T::regs();
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r.txd.ptr.write(|w|
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// We're giving the register a pointer to the stack. Since we're
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// waiting for the I2C transaction to end before this stack pointer
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// becomes invalid, there's nothing wrong here.
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//
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// The PTR field is a full 32 bits wide and accepts the full range
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// of values.
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w.ptr().bits(buffer.as_ptr() as u32));
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r.txd.maxcnt.write(|w|
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// We're giving it the length of the buffer, so no danger of
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// accessing invalid memory. We have verified that the length of the
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// buffer fits in an `u8`, so the cast to `u8` is also fine.
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//
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// The MAXCNT field is 8 bits wide and accepts the full range of
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// values.
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w.maxcnt().bits(buffer.len() as _));
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Ok(())
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}
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/// Set RX buffer, checking that it has suitable length.
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unsafe fn set_rx_buffer(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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// NOTE: RAM slice check is not necessary, as a mutable
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// slice can only be built from data located in RAM.
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::RxBufferTooLong);
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}
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let r = T::regs();
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r.rxd.ptr.write(|w|
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// We're giving the register a pointer to the stack. Since we're
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// waiting for the I2C transaction to end before this stack pointer
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// becomes invalid, there's nothing wrong here.
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//
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// The PTR field is a full 32 bits wide and accepts the full range
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// of values.
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w.ptr().bits(buffer.as_mut_ptr() as u32));
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r.rxd.maxcnt.write(|w|
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// We're giving it the length of the buffer, so no danger of
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// accessing invalid memory. We have verified that the length of the
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// buffer fits in an `u8`, so the cast to the type of maxcnt
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// is also fine.
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//
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// Note that that nrf52840 maxcnt is a wider
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// type than a u8, so we use a `_` cast rather than a `u8` cast.
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// The MAXCNT field is thus at least 8 bits wide and accepts the
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// full range of values that fit in a `u8`.
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w.maxcnt().bits(buffer.len() as _));
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Ok(())
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}
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fn clear_errorsrc(&mut self) {
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let r = T::regs();
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r.errorsrc
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.write(|w| w.anack().bit(true).dnack().bit(true).overrun().bit(true));
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}
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/// Get Error instance, if any occurred.
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fn check_errorsrc(&self) -> Result<(), Error> {
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let r = T::regs();
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let err = r.errorsrc.read();
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if err.anack().is_received() {
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return Err(Error::AddressNack);
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}
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if err.dnack().is_received() {
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return Err(Error::DataNack);
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}
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if err.overrun().is_received() {
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return Err(Error::Overrun);
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}
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Ok(())
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}
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fn check_rx(&self, len: usize) -> Result<(), Error> {
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let r = T::regs();
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if r.rxd.amount.read().bits() != len as u32 {
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Err(Error::Receive)
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} else {
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Ok(())
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}
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}
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fn check_tx(&self, len: usize) -> Result<(), Error> {
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let r = T::regs();
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if r.txd.amount.read().bits() != len as u32 {
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Err(Error::Transmit)
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} else {
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Ok(())
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}
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}
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/// Wait for stop or error
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fn blocking_wait(&mut self) {
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let r = T::regs();
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loop {
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if r.events_stopped.read().bits() != 0 {
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r.events_stopped.reset();
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break;
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}
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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}
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}
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/// Wait for stop or error
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#[cfg(feature = "time")]
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fn blocking_wait_timeout(&mut self, timeout: Duration) -> Result<(), Error> {
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let r = T::regs();
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let deadline = Instant::now() + timeout;
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loop {
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if r.events_stopped.read().bits() != 0 {
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r.events_stopped.reset();
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break;
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}
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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if Instant::now() > deadline {
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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return Err(Error::Timeout);
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}
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}
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Ok(())
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}
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/// Wait for stop or error
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fn async_wait(&mut self) -> impl Future<Output = ()> {
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poll_fn(move |cx| {
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let r = T::regs();
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let s = T::state();
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s.end_waker.register(cx.waker());
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if r.events_stopped.read().bits() != 0 {
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r.events_stopped.reset();
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return Poll::Ready(());
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}
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// stop if an error occurred
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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Poll::Pending
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})
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}
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fn setup_write_from_ram(&mut self, address: u8, buffer: &[u8], inten: bool) -> Result<(), Error> {
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let r = T::regs();
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compiler_fence(SeqCst);
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up the DMA write.
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unsafe { self.set_tx_buffer(buffer)? };
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// Clear events
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r.events_stopped.reset();
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r.events_error.reset();
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r.events_lasttx.reset();
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self.clear_errorsrc();
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if inten {
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r.intenset.write(|w| w.stopped().set().error().set());
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} else {
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r.intenclr.write(|w| w.stopped().clear().error().clear());
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}
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// Start write operation.
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r.shorts.write(|w| w.lasttx_stop().enabled());
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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if buffer.len() == 0 {
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// With a zero-length buffer, LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves.
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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Ok(())
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}
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fn setup_read(&mut self, address: u8, buffer: &mut [u8], inten: bool) -> Result<(), Error> {
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let r = T::regs();
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compiler_fence(SeqCst);
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up the DMA read.
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unsafe { self.set_rx_buffer(buffer)? };
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// Clear events
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r.events_stopped.reset();
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r.events_error.reset();
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self.clear_errorsrc();
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if inten {
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r.intenset.write(|w| w.stopped().set().error().set());
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} else {
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r.intenclr.write(|w| w.stopped().clear().error().clear());
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}
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// Start read operation.
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r.shorts.write(|w| w.lastrx_stop().enabled());
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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if buffer.len() == 0 {
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// With a zero-length buffer, LASTRX doesn't fire (because there's no last byte!), so do the STOP ourselves.
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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Ok(())
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}
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fn setup_write_read_from_ram(
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&mut self,
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address: u8,
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wr_buffer: &[u8],
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rd_buffer: &mut [u8],
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inten: bool,
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) -> Result<(), Error> {
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let r = T::regs();
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compiler_fence(SeqCst);
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up DMA buffers.
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unsafe {
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self.set_tx_buffer(wr_buffer)?;
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self.set_rx_buffer(rd_buffer)?;
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}
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// Clear events
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r.events_stopped.reset();
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r.events_error.reset();
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self.clear_errorsrc();
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if inten {
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r.intenset.write(|w| w.stopped().set().error().set());
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} else {
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r.intenclr.write(|w| w.stopped().clear().error().clear());
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}
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// Start write+read operation.
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r.shorts.write(|w| {
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w.lasttx_startrx().enabled();
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w.lastrx_stop().enabled();
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w
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});
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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if wr_buffer.len() == 0 && rd_buffer.len() == 0 {
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// With a zero-length buffer, LASTRX/LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves.
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// TODO handle when only one of the buffers is zero length
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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Ok(())
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}
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fn setup_write_read(
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&mut self,
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address: u8,
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wr_buffer: &[u8],
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rd_buffer: &mut [u8],
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inten: bool,
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) -> Result<(), Error> {
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match self.setup_write_read_from_ram(address, wr_buffer, rd_buffer, inten) {
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Ok(_) => Ok(()),
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Err(Error::BufferNotInRAM) => {
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trace!("Copying TWIM tx buffer into RAM for DMA");
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let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
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tx_ram_buf.copy_from_slice(wr_buffer);
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self.setup_write_read_from_ram(address, &tx_ram_buf, rd_buffer, inten)
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}
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Err(error) => Err(error),
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}
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}
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|
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fn setup_write(&mut self, address: u8, wr_buffer: &[u8], inten: bool) -> Result<(), Error> {
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match self.setup_write_from_ram(address, wr_buffer, inten) {
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Ok(_) => Ok(()),
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Err(Error::BufferNotInRAM) => {
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trace!("Copying TWIM tx buffer into RAM for DMA");
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let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
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tx_ram_buf.copy_from_slice(wr_buffer);
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self.setup_write_from_ram(address, &tx_ram_buf, inten)
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}
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Err(error) => Err(error),
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}
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}
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|
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/// Write to an I2C slave.
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///
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub fn blocking_write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
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self.setup_write(address, buffer, false)?;
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self.blocking_wait();
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compiler_fence(SeqCst);
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self.check_errorsrc()?;
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self.check_tx(buffer.len())?;
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Ok(())
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}
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/// Same as [`blocking_write`](Twim::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub fn blocking_write_from_ram(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
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self.setup_write_from_ram(address, buffer, false)?;
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self.blocking_wait();
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compiler_fence(SeqCst);
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self.check_errorsrc()?;
|
|
self.check_tx(buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Read from an I2C slave.
|
|
///
|
|
/// The buffer must have a length of at most 255 bytes on the nRF52832
|
|
/// and at most 65535 bytes on the nRF52840.
|
|
pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.setup_read(address, buffer, false)?;
|
|
self.blocking_wait();
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_rx(buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Write data to an I2C slave, then read data from the slave without
|
|
/// triggering a stop condition between the two.
|
|
///
|
|
/// The buffers must have a length of at most 255 bytes on the nRF52832
|
|
/// and at most 65535 bytes on the nRF52840.
|
|
pub fn blocking_write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.setup_write_read(address, wr_buffer, rd_buffer, false)?;
|
|
self.blocking_wait();
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(wr_buffer.len())?;
|
|
self.check_rx(rd_buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Same as [`blocking_write_read`](Twim::blocking_write_read) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
|
pub fn blocking_write_read_from_ram(
|
|
&mut self,
|
|
address: u8,
|
|
wr_buffer: &[u8],
|
|
rd_buffer: &mut [u8],
|
|
) -> Result<(), Error> {
|
|
self.setup_write_read_from_ram(address, wr_buffer, rd_buffer, false)?;
|
|
self.blocking_wait();
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(wr_buffer.len())?;
|
|
self.check_rx(rd_buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
// ===========================================
|
|
|
|
/// Write to an I2C slave with timeout.
|
|
///
|
|
/// See [`blocking_write`].
|
|
#[cfg(feature = "time")]
|
|
pub fn blocking_write_timeout(&mut self, address: u8, buffer: &[u8], timeout: Duration) -> Result<(), Error> {
|
|
self.setup_write(address, buffer, false)?;
|
|
self.blocking_wait_timeout(timeout)?;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Same as [`blocking_write`](Twim::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
|
#[cfg(feature = "time")]
|
|
pub fn blocking_write_from_ram_timeout(
|
|
&mut self,
|
|
address: u8,
|
|
buffer: &[u8],
|
|
timeout: Duration,
|
|
) -> Result<(), Error> {
|
|
self.setup_write_from_ram(address, buffer, false)?;
|
|
self.blocking_wait_timeout(timeout)?;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Read from an I2C slave.
|
|
///
|
|
/// The buffer must have a length of at most 255 bytes on the nRF52832
|
|
/// and at most 65535 bytes on the nRF52840.
|
|
#[cfg(feature = "time")]
|
|
pub fn blocking_read_timeout(&mut self, address: u8, buffer: &mut [u8], timeout: Duration) -> Result<(), Error> {
|
|
self.setup_read(address, buffer, false)?;
|
|
self.blocking_wait_timeout(timeout)?;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_rx(buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Write data to an I2C slave, then read data from the slave without
|
|
/// triggering a stop condition between the two.
|
|
///
|
|
/// The buffers must have a length of at most 255 bytes on the nRF52832
|
|
/// and at most 65535 bytes on the nRF52840.
|
|
#[cfg(feature = "time")]
|
|
pub fn blocking_write_read_timeout(
|
|
&mut self,
|
|
address: u8,
|
|
wr_buffer: &[u8],
|
|
rd_buffer: &mut [u8],
|
|
timeout: Duration,
|
|
) -> Result<(), Error> {
|
|
self.setup_write_read(address, wr_buffer, rd_buffer, false)?;
|
|
self.blocking_wait_timeout(timeout)?;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(wr_buffer.len())?;
|
|
self.check_rx(rd_buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Same as [`blocking_write_read`](Twim::blocking_write_read) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
|
#[cfg(feature = "time")]
|
|
pub fn blocking_write_read_from_ram_timeout(
|
|
&mut self,
|
|
address: u8,
|
|
wr_buffer: &[u8],
|
|
rd_buffer: &mut [u8],
|
|
timeout: Duration,
|
|
) -> Result<(), Error> {
|
|
self.setup_write_read_from_ram(address, wr_buffer, rd_buffer, false)?;
|
|
self.blocking_wait_timeout(timeout)?;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(wr_buffer.len())?;
|
|
self.check_rx(rd_buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
// ===========================================
|
|
|
|
/// Read from an I2C slave.
|
|
///
|
|
/// The buffer must have a length of at most 255 bytes on the nRF52832
|
|
/// and at most 65535 bytes on the nRF52840.
|
|
pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.setup_read(address, buffer, true)?;
|
|
self.async_wait().await;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_rx(buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Write to an I2C slave.
|
|
///
|
|
/// The buffer must have a length of at most 255 bytes on the nRF52832
|
|
/// and at most 65535 bytes on the nRF52840.
|
|
pub async fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
|
|
self.setup_write(address, buffer, true)?;
|
|
self.async_wait().await;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Same as [`write`](Twim::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
|
pub async fn write_from_ram(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
|
|
self.setup_write_from_ram(address, buffer, true)?;
|
|
self.async_wait().await;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Write data to an I2C slave, then read data from the slave without
|
|
/// triggering a stop condition between the two.
|
|
///
|
|
/// The buffers must have a length of at most 255 bytes on the nRF52832
|
|
/// and at most 65535 bytes on the nRF52840.
|
|
pub async fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.setup_write_read(address, wr_buffer, rd_buffer, true)?;
|
|
self.async_wait().await;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(wr_buffer.len())?;
|
|
self.check_rx(rd_buffer.len())?;
|
|
Ok(())
|
|
}
|
|
|
|
/// Same as [`write_read`](Twim::write_read) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
|
pub async fn write_read_from_ram(
|
|
&mut self,
|
|
address: u8,
|
|
wr_buffer: &[u8],
|
|
rd_buffer: &mut [u8],
|
|
) -> Result<(), Error> {
|
|
self.setup_write_read_from_ram(address, wr_buffer, rd_buffer, true)?;
|
|
self.async_wait().await;
|
|
compiler_fence(SeqCst);
|
|
self.check_errorsrc()?;
|
|
self.check_tx(wr_buffer.len())?;
|
|
self.check_rx(rd_buffer.len())?;
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'a, T: Instance> Drop for Twim<'a, T> {
|
|
fn drop(&mut self) {
|
|
trace!("twim drop");
|
|
|
|
// TODO: check for abort
|
|
|
|
// disable!
|
|
let r = T::regs();
|
|
r.enable.write(|w| w.enable().disabled());
|
|
|
|
gpio::deconfigure_pin(r.psel.sda.read().bits());
|
|
gpio::deconfigure_pin(r.psel.scl.read().bits());
|
|
|
|
trace!("twim drop: done");
|
|
}
|
|
}
|
|
|
|
pub(crate) mod sealed {
|
|
use super::*;
|
|
|
|
pub struct State {
|
|
pub end_waker: AtomicWaker,
|
|
}
|
|
|
|
impl State {
|
|
pub const fn new() -> Self {
|
|
Self {
|
|
end_waker: AtomicWaker::new(),
|
|
}
|
|
}
|
|
}
|
|
|
|
pub trait Instance {
|
|
fn regs() -> &'static pac::twim0::RegisterBlock;
|
|
fn state() -> &'static State;
|
|
}
|
|
}
|
|
|
|
/// TWIM peripheral instance.
|
|
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
|
|
/// Interrupt for this peripheral.
|
|
type Interrupt: interrupt::typelevel::Interrupt;
|
|
}
|
|
|
|
macro_rules! impl_twim {
|
|
($type:ident, $pac_type:ident, $irq:ident) => {
|
|
impl crate::twim::sealed::Instance for peripherals::$type {
|
|
fn regs() -> &'static pac::twim0::RegisterBlock {
|
|
unsafe { &*pac::$pac_type::ptr() }
|
|
}
|
|
fn state() -> &'static crate::twim::sealed::State {
|
|
static STATE: crate::twim::sealed::State = crate::twim::sealed::State::new();
|
|
&STATE
|
|
}
|
|
}
|
|
impl crate::twim::Instance for peripherals::$type {
|
|
type Interrupt = crate::interrupt::typelevel::$irq;
|
|
}
|
|
};
|
|
}
|
|
|
|
// ====================
|
|
|
|
mod eh02 {
|
|
use super::*;
|
|
|
|
impl<'a, T: Instance> embedded_hal_02::blocking::i2c::Write for Twim<'a, T> {
|
|
type Error = Error;
|
|
|
|
fn write<'w>(&mut self, addr: u8, bytes: &'w [u8]) -> Result<(), Error> {
|
|
if slice_in_ram(bytes) {
|
|
self.blocking_write(addr, bytes)
|
|
} else {
|
|
let buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..];
|
|
for chunk in bytes.chunks(FORCE_COPY_BUFFER_SIZE) {
|
|
buf[..chunk.len()].copy_from_slice(chunk);
|
|
self.blocking_write(addr, &buf[..chunk.len()])?;
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'a, T: Instance> embedded_hal_02::blocking::i2c::Read for Twim<'a, T> {
|
|
type Error = Error;
|
|
|
|
fn read<'w>(&mut self, addr: u8, bytes: &'w mut [u8]) -> Result<(), Error> {
|
|
self.blocking_read(addr, bytes)
|
|
}
|
|
}
|
|
|
|
impl<'a, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for Twim<'a, T> {
|
|
type Error = Error;
|
|
|
|
fn write_read<'w>(&mut self, addr: u8, bytes: &'w [u8], buffer: &'w mut [u8]) -> Result<(), Error> {
|
|
self.blocking_write_read(addr, bytes, buffer)
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "unstable-traits")]
|
|
mod eh1 {
|
|
use super::*;
|
|
|
|
impl embedded_hal_1::i2c::Error for Error {
|
|
fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
|
|
match *self {
|
|
Self::TxBufferTooLong => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::RxBufferTooLong => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::Transmit => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::Receive => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::BufferNotInRAM => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::AddressNack => {
|
|
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address)
|
|
}
|
|
Self::DataNack => {
|
|
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Data)
|
|
}
|
|
Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
|
|
Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::i2c::ErrorType for Twim<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::i2c::I2c for Twim<'d, T> {
|
|
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_read(address, buffer)
|
|
}
|
|
|
|
fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(address, buffer)
|
|
}
|
|
|
|
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write_read(address, wr_buffer, rd_buffer)
|
|
}
|
|
|
|
fn transaction<'a>(
|
|
&mut self,
|
|
_address: u8,
|
|
_operations: &mut [embedded_hal_1::i2c::Operation<'a>],
|
|
) -> Result<(), Self::Error> {
|
|
todo!();
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
|
|
mod eha {
|
|
use super::*;
|
|
impl<'d, T: Instance> embedded_hal_async::i2c::I2c for Twim<'d, T> {
|
|
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.read(address, read).await
|
|
}
|
|
|
|
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
|
|
self.write(address, write).await
|
|
}
|
|
async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.write_read(address, write, read).await
|
|
}
|
|
|
|
async fn transaction(
|
|
&mut self,
|
|
address: u8,
|
|
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
|
|
) -> Result<(), Self::Error> {
|
|
let _ = address;
|
|
let _ = operations;
|
|
todo!()
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> SetConfig for Twim<'d, T> {
|
|
type Config = Config;
|
|
fn set_config(&mut self, config: &Self::Config) {
|
|
let r = T::regs();
|
|
r.frequency
|
|
.write(|w| unsafe { w.frequency().bits(config.frequency as u32) });
|
|
}
|
|
}
|