921780e6bf
- Move typelevel interrupts to a special-purpose mod: `embassy_xx::interrupt::typelevel`. - Reexport the PAC interrupt enum in `embassy_xx::interrupt`. This has a few advantages: - The `embassy_xx::interrupt` module is now more "standard". - It works with `cortex-m` functions for manipulating interrupts, for example. - It works with RTIC. - the interrupt enum allows holding value that can be "any interrupt at runtime", this can't be done with typelevel irqs. - When "const-generics on enums" is stable, we can remove the typelevel interrupts without disruptive changes to `embassy_xx::interrupt`.
333 lines
10 KiB
Rust
333 lines
10 KiB
Rust
use core::cell::Cell;
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use core::convert::TryInto;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::{mem, ptr};
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use atomic_polyfill::{AtomicU32, AtomicU8};
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use critical_section::CriticalSection;
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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use embassy_sync::blocking_mutex::Mutex;
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use embassy_time::driver::{AlarmHandle, Driver};
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use embassy_time::TICK_HZ;
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use stm32_metapac::timer::regs;
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use crate::interrupt::typelevel::Interrupt;
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use crate::pac::timer::vals;
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use crate::rcc::sealed::RccPeripheral;
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use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance};
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use crate::{interrupt, peripherals};
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#[cfg(not(any(time_driver_tim12, time_driver_tim15)))]
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const ALARM_COUNT: usize = 3;
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#[cfg(any(time_driver_tim12, time_driver_tim15))]
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const ALARM_COUNT: usize = 1;
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#[cfg(time_driver_tim2)]
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type T = peripherals::TIM2;
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#[cfg(time_driver_tim3)]
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type T = peripherals::TIM3;
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#[cfg(time_driver_tim4)]
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type T = peripherals::TIM4;
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#[cfg(time_driver_tim5)]
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type T = peripherals::TIM5;
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#[cfg(time_driver_tim12)]
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type T = peripherals::TIM12;
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#[cfg(time_driver_tim15)]
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type T = peripherals::TIM15;
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foreach_interrupt! {
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(TIM2, timer, $block:ident, UP, $irq:ident) => {
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#[cfg(time_driver_tim2)]
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#[interrupt]
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fn $irq() {
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DRIVER.on_interrupt()
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}
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};
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(TIM3, timer, $block:ident, UP, $irq:ident) => {
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#[cfg(time_driver_tim3)]
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#[interrupt]
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fn $irq() {
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DRIVER.on_interrupt()
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}
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};
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(TIM4, timer, $block:ident, UP, $irq:ident) => {
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#[cfg(time_driver_tim4)]
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#[interrupt]
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fn $irq() {
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DRIVER.on_interrupt()
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}
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};
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(TIM5, timer, $block:ident, UP, $irq:ident) => {
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#[cfg(time_driver_tim5)]
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#[interrupt]
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fn $irq() {
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DRIVER.on_interrupt()
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}
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};
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(TIM12, timer, $block:ident, UP, $irq:ident) => {
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#[cfg(time_driver_tim12)]
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#[interrupt]
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fn $irq() {
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DRIVER.on_interrupt()
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}
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};
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(TIM15, timer, $block:ident, UP, $irq:ident) => {
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#[cfg(time_driver_tim15)]
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#[interrupt]
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fn $irq() {
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DRIVER.on_interrupt()
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}
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};
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}
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// Clock timekeeping works with something we call "periods", which are time intervals
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// of 2^15 ticks. The Clock counter value is 16 bits, so one "overflow cycle" is 2 periods.
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//
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// A `period` count is maintained in parallel to the Timer hardware `counter`, like this:
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// - `period` and `counter` start at 0
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// - `period` is incremented on overflow (at counter value 0)
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// - `period` is incremented "midway" between overflows (at counter value 0x8000)
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//
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// Therefore, when `period` is even, counter is in 0..0x7FFF. When odd, counter is in 0x8000..0xFFFF
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// This allows for now() to return the correct value even if it races an overflow.
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//
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// To get `now()`, `period` is read first, then `counter` is read. If the counter value matches
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// the expected range for the `period` parity, we're done. If it doesn't, this means that
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// a new period start has raced us between reading `period` and `counter`, so we assume the `counter` value
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// corresponds to the next period.
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//
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// `period` is a 32bit integer, so It overflows on 2^32 * 2^15 / 32768 seconds of uptime, which is 136 years.
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fn calc_now(period: u32, counter: u16) -> u64 {
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((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
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}
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struct AlarmState {
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timestamp: Cell<u64>,
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// This is really a Option<(fn(*mut ()), *mut ())>
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// but fn pointers aren't allowed in const yet
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callback: Cell<*const ()>,
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ctx: Cell<*mut ()>,
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}
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unsafe impl Send for AlarmState {}
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impl AlarmState {
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const fn new() -> Self {
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Self {
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timestamp: Cell::new(u64::MAX),
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callback: Cell::new(ptr::null()),
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ctx: Cell::new(ptr::null_mut()),
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}
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}
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}
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struct RtcDriver {
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/// Number of 2^15 periods elapsed since boot.
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period: AtomicU32,
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alarm_count: AtomicU8,
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/// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
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alarms: Mutex<CriticalSectionRawMutex, [AlarmState; ALARM_COUNT]>,
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}
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const ALARM_STATE_NEW: AlarmState = AlarmState::new();
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embassy_time::time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
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period: AtomicU32::new(0),
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alarm_count: AtomicU8::new(0),
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alarms: Mutex::const_new(CriticalSectionRawMutex::new(), [ALARM_STATE_NEW; ALARM_COUNT]),
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});
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impl RtcDriver {
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fn init(&'static self) {
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let r = T::regs_gp16();
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<T as RccPeripheral>::enable();
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<T as RccPeripheral>::reset();
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let timer_freq = T::frequency();
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// NOTE(unsafe) Critical section to use the unsafe methods
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critical_section::with(|_| unsafe {
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r.cr1().modify(|w| w.set_cen(false));
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r.cnt().write(|w| w.set_cnt(0));
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let psc = timer_freq.0 / TICK_HZ as u32 - 1;
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let psc: u16 = match psc.try_into() {
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Err(_) => panic!("psc division overflow: {}", psc),
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Ok(n) => n,
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};
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r.psc().write(|w| w.set_psc(psc));
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r.arr().write(|w| w.set_arr(u16::MAX));
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// Set URS, generate update and clear URS
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r.cr1().modify(|w| w.set_urs(vals::Urs::COUNTERONLY));
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r.egr().write(|w| w.set_ug(true));
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r.cr1().modify(|w| w.set_urs(vals::Urs::ANYEVENT));
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// Mid-way point
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r.ccr(0).write(|w| w.set_ccr(0x8000));
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// Enable overflow and half-overflow interrupts
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r.dier().write(|w| {
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w.set_uie(true);
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w.set_ccie(0, true);
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});
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<T as BasicInstance>::Interrupt::unpend();
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<T as BasicInstance>::Interrupt::enable();
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r.cr1().modify(|w| w.set_cen(true));
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})
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}
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fn on_interrupt(&self) {
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let r = T::regs_gp16();
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// NOTE(unsafe) Use critical section to access the methods
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// XXX: reduce the size of this critical section ?
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critical_section::with(|cs| unsafe {
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let sr = r.sr().read();
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let dier = r.dier().read();
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// Clear all interrupt flags. Bits in SR are "write 0 to clear", so write the bitwise NOT.
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// Other approaches such as writing all zeros, or RMWing won't work, they can
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// miss interrupts.
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r.sr().write_value(regs::SrGp(!sr.0));
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// Overflow
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if sr.uif() {
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self.next_period();
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}
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// Half overflow
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if sr.ccif(0) {
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self.next_period();
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}
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for n in 0..ALARM_COUNT {
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if sr.ccif(n + 1) && dier.ccie(n + 1) {
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self.trigger_alarm(n, cs);
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}
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}
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})
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}
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fn next_period(&self) {
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let r = T::regs_gp16();
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let period = self.period.fetch_add(1, Ordering::Relaxed) + 1;
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let t = (period as u64) << 15;
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critical_section::with(move |cs| unsafe {
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r.dier().modify(move |w| {
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for n in 0..ALARM_COUNT {
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let alarm = &self.alarms.borrow(cs)[n];
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let at = alarm.timestamp.get();
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if at < t + 0xc000 {
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// just enable it. `set_alarm` has already set the correct CCR val.
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w.set_ccie(n + 1, true);
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}
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}
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})
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})
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}
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fn get_alarm<'a>(&'a self, cs: CriticalSection<'a>, alarm: AlarmHandle) -> &'a AlarmState {
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// safety: we're allowed to assume the AlarmState is created by us, and
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// we never create one that's out of bounds.
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unsafe { self.alarms.borrow(cs).get_unchecked(alarm.id() as usize) }
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}
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fn trigger_alarm(&self, n: usize, cs: CriticalSection) {
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let alarm = &self.alarms.borrow(cs)[n];
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alarm.timestamp.set(u64::MAX);
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// Call after clearing alarm, so the callback can set another alarm.
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// safety:
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// - we can ignore the possibility of `f` being unset (null) because of the safety contract of `allocate_alarm`.
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// - other than that we only store valid function pointers into alarm.callback
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let f: fn(*mut ()) = unsafe { mem::transmute(alarm.callback.get()) };
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f(alarm.ctx.get());
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}
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}
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impl Driver for RtcDriver {
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fn now(&self) -> u64 {
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let r = T::regs_gp16();
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let period = self.period.load(Ordering::Relaxed);
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compiler_fence(Ordering::Acquire);
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// NOTE(unsafe) Atomic read with no side-effects
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let counter = unsafe { r.cnt().read().cnt() };
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calc_now(period, counter)
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}
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unsafe fn allocate_alarm(&self) -> Option<AlarmHandle> {
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let id = self.alarm_count.fetch_update(Ordering::AcqRel, Ordering::Acquire, |x| {
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if x < ALARM_COUNT as u8 {
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Some(x + 1)
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} else {
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None
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}
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});
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match id {
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Ok(id) => Some(AlarmHandle::new(id)),
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Err(_) => None,
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}
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}
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fn set_alarm_callback(&self, alarm: AlarmHandle, callback: fn(*mut ()), ctx: *mut ()) {
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critical_section::with(|cs| {
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let alarm = self.get_alarm(cs, alarm);
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alarm.callback.set(callback as *const ());
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alarm.ctx.set(ctx);
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})
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}
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fn set_alarm(&self, alarm: AlarmHandle, timestamp: u64) -> bool {
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critical_section::with(|cs| {
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let r = T::regs_gp16();
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let n = alarm.id() as usize;
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let alarm = self.get_alarm(cs, alarm);
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alarm.timestamp.set(timestamp);
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let t = self.now();
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if timestamp <= t {
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// If alarm timestamp has passed the alarm will not fire.
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// Disarm the alarm and return `false` to indicate that.
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unsafe { r.dier().modify(|w| w.set_ccie(n + 1, false)) };
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alarm.timestamp.set(u64::MAX);
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return false;
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}
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let safe_timestamp = timestamp.max(t + 3);
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// Write the CCR value regardless of whether we're going to enable it now or not.
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// This way, when we enable it later, the right value is already set.
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unsafe { r.ccr(n + 1).write(|w| w.set_ccr(safe_timestamp as u16)) };
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// Enable it if it'll happen soon. Otherwise, `next_period` will enable it.
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let diff = timestamp - t;
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// NOTE(unsafe) We're in a critical section
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unsafe { r.dier().modify(|w| w.set_ccie(n + 1, diff < 0xc000)) };
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true
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})
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}
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}
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pub(crate) fn init() {
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DRIVER.init()
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}
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