70 lines
2.1 KiB
Rust
70 lines
2.1 KiB
Rust
//! Universal Serial Bus (USB)
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#[cfg_attr(usb, path = "usb.rs")]
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#[cfg_attr(otg, path = "otg.rs")]
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mod _version;
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pub use _version::*;
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use crate::interrupt::typelevel::Interrupt;
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use crate::rcc;
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/// clock, power initialization stuff that's common for USB and OTG.
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fn common_init<T: Instance>() {
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// Check the USB clock is enabled and running at exactly 48 MHz.
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// frequency() will panic if not enabled
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let freq = T::frequency();
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// Check frequency is within the 0.25% tolerance allowed by the spec.
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// Clock might not be exact 48Mhz due to rounding errors in PLL calculation, or if the user
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// has tight clock restrictions due to something else (like audio).
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if freq.0.abs_diff(48_000_000) > 120_000 {
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panic!(
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"USB clock should be 48Mhz but is {} Hz. Please double-check your RCC settings.",
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freq.0
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)
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}
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#[cfg(any(stm32l4, stm32l5, stm32wb, stm32u0))]
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critical_section::with(|_| crate::pac::PWR.cr2().modify(|w| w.set_usv(true)));
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#[cfg(pwr_h5)]
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critical_section::with(|_| crate::pac::PWR.usbscr().modify(|w| w.set_usb33sv(true)));
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#[cfg(stm32h7)]
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{
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// If true, VDD33USB is generated by internal regulator from VDD50USB
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// If false, VDD33USB and VDD50USB must be suplied directly with 3.3V (default on nucleo)
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// TODO: unhardcode
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let internal_regulator = false;
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// Enable USB power
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critical_section::with(|_| {
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crate::pac::PWR.cr3().modify(|w| {
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w.set_usb33den(true);
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w.set_usbregen(internal_regulator);
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})
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});
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// Wait for USB power to stabilize
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while !crate::pac::PWR.cr3().read().usb33rdy() {}
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}
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#[cfg(stm32u5)]
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{
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// Enable USB power
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critical_section::with(|_| {
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crate::pac::PWR.svmcr().modify(|w| {
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w.set_usv(true);
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w.set_uvmen(true);
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})
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});
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// Wait for USB power to stabilize
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while !crate::pac::PWR.svmsr().read().vddusbrdy() {}
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}
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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rcc::enable_and_reset::<T>();
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}
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