435 lines
14 KiB
Rust
435 lines
14 KiB
Rust
//! Quad Serial Peripheral Interface (QSPI)
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#![macro_use]
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pub mod enums;
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use core::marker::PhantomData;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use enums::*;
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use crate::dma::ChannelAndRequest;
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use crate::gpio::{AfType, AnyPin, OutputType, Pull, Speed};
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use crate::mode::{Async, Blocking, Mode as PeriMode};
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use crate::pac::quadspi::Quadspi as Regs;
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use crate::rcc::{self, RccPeripheral};
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use crate::{peripherals, Peripheral};
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/// QSPI transfer configuration.
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pub struct TransferConfig {
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/// Instraction width (IMODE)
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pub iwidth: QspiWidth,
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/// Address width (ADMODE)
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pub awidth: QspiWidth,
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/// Data width (DMODE)
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pub dwidth: QspiWidth,
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/// Instruction Id
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pub instruction: u8,
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/// Flash memory address
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pub address: Option<u32>,
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/// Number of dummy cycles (DCYC)
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pub dummy: DummyCycles,
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}
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impl Default for TransferConfig {
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fn default() -> Self {
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Self {
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iwidth: QspiWidth::NONE,
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awidth: QspiWidth::NONE,
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dwidth: QspiWidth::NONE,
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instruction: 0,
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address: None,
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dummy: DummyCycles::_0,
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}
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}
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}
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/// QSPI driver configuration.
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pub struct Config {
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/// Flash memory size representend as 2^[0-32], as reasonable minimum 1KiB(9) was chosen.
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/// If you need other value the whose predefined use `Other` variant.
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pub memory_size: MemorySize,
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/// Address size (8/16/24/32-bit)
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pub address_size: AddressSize,
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/// Scalar factor for generating CLK [0-255]
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pub prescaler: u8,
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/// Number of bytes to trigger FIFO threshold flag.
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pub fifo_threshold: FIFOThresholdLevel,
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/// Minimum number of cycles that chip select must be high between issued commands
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pub cs_high_time: ChipSelectHighTime,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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memory_size: MemorySize::Other(0),
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address_size: AddressSize::_24bit,
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prescaler: 128,
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fifo_threshold: FIFOThresholdLevel::_17Bytes,
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cs_high_time: ChipSelectHighTime::_5Cycle,
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}
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}
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}
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/// QSPI driver.
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#[allow(dead_code)]
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pub struct Qspi<'d, T: Instance, M: PeriMode> {
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_peri: PeripheralRef<'d, T>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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d1: Option<PeripheralRef<'d, AnyPin>>,
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dma: Option<ChannelAndRequest<'d>>,
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_phantom: PhantomData<M>,
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config: Config,
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}
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impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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d1: Option<PeripheralRef<'d, AnyPin>>,
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dma: Option<ChannelAndRequest<'d>>,
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config: Config,
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fsel: FlashSelection,
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) -> Self {
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into_ref!(peri);
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rcc::enable_and_reset::<T>();
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while T::REGS.sr().read().busy() {}
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#[cfg(stm32h7)]
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{
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use stm32_metapac::quadspi::regs::Cr;
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// Apply precautionary steps according to the errata...
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T::REGS.cr().write_value(Cr(0));
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while T::REGS.sr().read().busy() {}
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T::REGS.cr().write_value(Cr(0xFF000001));
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T::REGS.ccr().write(|w| w.set_frcm(true));
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T::REGS.ccr().write(|w| w.set_frcm(true));
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T::REGS.cr().write_value(Cr(0));
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while T::REGS.sr().read().busy() {}
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}
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T::REGS.cr().modify(|w| {
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w.set_en(true);
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//w.set_tcen(false);
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w.set_sshift(false);
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w.set_fthres(config.fifo_threshold.into());
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w.set_prescaler(config.prescaler);
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w.set_fsel(fsel.into());
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});
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T::REGS.dcr().modify(|w| {
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w.set_fsize(config.memory_size.into());
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w.set_csht(config.cs_high_time.into());
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w.set_ckmode(true);
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});
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Self {
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_peri: peri,
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sck,
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d0,
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d1,
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d2,
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d3,
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nss,
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dma,
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_phantom: PhantomData,
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config,
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}
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}
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/// Do a QSPI command.
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pub fn command(&mut self, transaction: TransferConfig) {
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, None);
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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/// Blocking read data.
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pub fn blocking_read(&mut self, buf: &mut [u8], transaction: TransferConfig) {
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
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let current_ar = T::REGS.ar().read().address();
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectRead.into());
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});
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T::REGS.ar().write(|v| {
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v.set_address(current_ar);
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});
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for b in buf {
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while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
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*b = unsafe { (T::REGS.dr().as_ptr() as *mut u8).read_volatile() };
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}
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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/// Blocking write data.
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pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) {
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// STM32H7 does not have dmaen
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectWrite.into());
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});
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for &b in buf {
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while !T::REGS.sr().read().ftf() {}
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unsafe { (T::REGS.dr().as_ptr() as *mut u8).write_volatile(b) };
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}
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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fn setup_transaction(&mut self, fmode: QspiMode, transaction: &TransferConfig, data_len: Option<usize>) {
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T::REGS.fcr().modify(|v| {
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v.set_csmf(true);
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v.set_ctcf(true);
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v.set_ctef(true);
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v.set_ctof(true);
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});
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while T::REGS.sr().read().busy() {}
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if let Some(len) = data_len {
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T::REGS.dlr().write(|v| v.set_dl(len as u32 - 1));
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}
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T::REGS.ccr().write(|v| {
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v.set_fmode(fmode.into());
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v.set_imode(transaction.iwidth.into());
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v.set_instruction(transaction.instruction);
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v.set_admode(transaction.awidth.into());
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v.set_adsize(self.config.address_size.into());
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v.set_dmode(transaction.dwidth.into());
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v.set_abmode(QspiWidth::NONE.into());
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v.set_dcyc(transaction.dummy.into());
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});
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if let Some(addr) = transaction.address {
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T::REGS.ar().write(|v| {
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v.set_address(addr);
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});
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}
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}
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}
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impl<'d, T: Instance> Qspi<'d, T, Blocking> {
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/// Create a new QSPI driver for bank 1, in blocking mode.
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pub fn new_blocking_bank1(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(
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nss,
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AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
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),
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None,
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config,
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FlashSelection::Flash1,
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)
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}
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/// Create a new QSPI driver for bank 2, in blocking mode.
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pub fn new_blocking_bank2(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(
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nss,
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AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
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),
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None,
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config,
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FlashSelection::Flash2,
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)
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}
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}
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impl<'d, T: Instance> Qspi<'d, T, Async> {
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/// Create a new QSPI driver for bank 1.
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pub fn new_bank1(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
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dma: impl Peripheral<P = impl QuadDma<T>> + 'd,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(
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nss,
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AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
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),
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new_dma!(dma),
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config,
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FlashSelection::Flash1,
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)
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}
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/// Create a new QSPI driver for bank 2.
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pub fn new_bank2(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
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dma: impl Peripheral<P = impl QuadDma<T>> + 'd,
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config: Config,
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) -> Self {
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Self::new_inner(
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peri,
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new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
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new_pin!(
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nss,
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AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
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),
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new_dma!(dma),
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config,
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FlashSelection::Flash2,
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)
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}
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/// Blocking read data, using DMA.
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pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectRead.into());
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});
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let current_ar = T::REGS.ar().read().address();
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T::REGS.ar().write(|v| {
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v.set_address(current_ar);
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});
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let transfer = unsafe {
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self.dma
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.as_mut()
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.unwrap()
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.read(T::REGS.dr().as_ptr() as *mut u8, buf, Default::default())
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};
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// STM32H7 does not have dmaen
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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transfer.blocking_wait();
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}
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/// Blocking write data, using DMA.
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pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
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self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectWrite.into());
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});
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let transfer = unsafe {
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self.dma
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.as_mut()
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.unwrap()
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.write(buf, T::REGS.dr().as_ptr() as *mut u8, Default::default())
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};
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// STM32H7 does not have dmaen
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#[cfg(not(stm32h7))]
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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transfer.blocking_wait();
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}
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}
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trait SealedInstance {
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const REGS: Regs;
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}
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/// QSPI instance trait.
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#[allow(private_bounds)]
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pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
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pin_trait!(SckPin, Instance);
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pin_trait!(BK1D0Pin, Instance);
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pin_trait!(BK1D1Pin, Instance);
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pin_trait!(BK1D2Pin, Instance);
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pin_trait!(BK1D3Pin, Instance);
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pin_trait!(BK1NSSPin, Instance);
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pin_trait!(BK2D0Pin, Instance);
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pin_trait!(BK2D1Pin, Instance);
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pin_trait!(BK2D2Pin, Instance);
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pin_trait!(BK2D3Pin, Instance);
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pin_trait!(BK2NSSPin, Instance);
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dma_trait!(QuadDma, Instance);
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foreach_peripheral!(
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(quadspi, $inst:ident) => {
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impl SealedInstance for peripherals::$inst {
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const REGS: Regs = crate::pac::$inst;
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}
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impl Instance for peripherals::$inst {}
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};
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);
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