1009 lines
32 KiB
Rust
1009 lines
32 KiB
Rust
//! HSPI Serial Peripheral Interface
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//!
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// NOTE: This is a partial implementation of the HSPI driver.
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// It implements only Single and Octal SPI modes, but additional
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// modes can be added as needed following the same pattern and
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// using ospi/mod.rs as a reference.
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#![macro_use]
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pub mod enums;
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use core::marker::PhantomData;
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use embassy_embedded_hal::{GetConfig, SetConfig};
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use embassy_hal_internal::{into_ref, PeripheralRef};
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pub use enums::*;
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use crate::dma::{word, ChannelAndRequest};
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use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
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use crate::mode::{Async, Blocking, Mode as PeriMode};
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use crate::pac::hspi::Hspi as Regs;
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use crate::rcc::{self, RccPeripheral};
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use crate::{peripherals, Peripheral};
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/// HSPI driver config.
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#[derive(Clone, Copy, defmt::Format)]
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pub struct Config {
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/// Fifo threshold used by the peripheral to generate the interrupt indicating data
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/// or space is available in the FIFO
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pub fifo_threshold: FIFOThresholdLevel,
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/// Indicates the type of external device connected
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pub memory_type: MemoryType, // Need to add an additional enum to provide this public interface
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/// Defines the size of the external device connected to the HSPI corresponding
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/// to the number of address bits required to access the device
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pub device_size: MemorySize,
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/// Sets the minimum number of clock cycles that the chip select signal must be held high
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/// between commands
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pub chip_select_high_time: ChipSelectHighTime,
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/// Enables the free running clock
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pub free_running_clock: bool,
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/// Sets the clock level when the device is not selected
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pub clock_mode: bool,
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/// Indicates the wrap size corresponding to the external device configuration
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pub wrap_size: WrapSize,
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/// Specified the prescaler factor used for generating the external clock based
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/// on the AHB clock
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pub clock_prescaler: u8,
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/// Allows the delay of 1/2 cycle the data sampling to account for external
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/// signal delays
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pub sample_shifting: bool,
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/// Allows hold to 1/4 cycle the data
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pub delay_hold_quarter_cycle: bool,
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/// Enables the transaction boundary feature and defines the boundary to release
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/// the chip select
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pub chip_select_boundary: u8,
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/// Enables the delay block bypass so the sampling is not affected by the delay block
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pub delay_block_bypass: bool,
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/// Enables communication regulation feature. Chip select is released when the other
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/// HSPI requests access to the bus
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pub max_transfer: u8,
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/// Enables the refresh feature, chip select is released every refresh + 1 clock cycles
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pub refresh: u32,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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fifo_threshold: FIFOThresholdLevel::_16Bytes,
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memory_type: MemoryType::Micron,
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device_size: MemorySize::Other(0),
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chip_select_high_time: ChipSelectHighTime::_5Cycle,
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free_running_clock: false,
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clock_mode: false,
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wrap_size: WrapSize::None,
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clock_prescaler: 0,
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sample_shifting: false,
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delay_hold_quarter_cycle: false,
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chip_select_boundary: 0, // Acceptable range 0 to 31
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delay_block_bypass: true,
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max_transfer: 0,
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refresh: 0,
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}
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}
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}
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/// HSPI transfer configuration.
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pub struct TransferConfig {
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/// Instruction width (IMODE)
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pub iwidth: HspiWidth,
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/// Instruction Id
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pub instruction: Option<u32>,
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/// Number of Instruction Bytes
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pub isize: AddressSize,
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/// Instruction Double Transfer rate enable
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pub idtr: bool,
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/// Address width (ADMODE)
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pub adwidth: HspiWidth,
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/// Device memory address
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pub address: Option<u32>,
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/// Number of Address Bytes
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pub adsize: AddressSize,
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/// Address Double Transfer rate enable
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pub addtr: bool,
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/// Alternate bytes width (ABMODE)
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pub abwidth: HspiWidth,
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/// Alternate Bytes
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pub alternate_bytes: Option<u32>,
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/// Number of Alternate Bytes
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pub absize: AddressSize,
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/// Alternate Bytes Double Transfer rate enable
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pub abdtr: bool,
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/// Data width (DMODE)
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pub dwidth: HspiWidth,
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/// Data buffer
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pub ddtr: bool,
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/// Number of dummy cycles (DCYC)
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pub dummy: DummyCycles,
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}
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impl Default for TransferConfig {
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fn default() -> Self {
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Self {
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iwidth: HspiWidth::NONE,
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instruction: None,
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isize: AddressSize::_8Bit,
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idtr: false,
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adwidth: HspiWidth::NONE,
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address: None,
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adsize: AddressSize::_8Bit,
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addtr: false,
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abwidth: HspiWidth::NONE,
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alternate_bytes: None,
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absize: AddressSize::_8Bit,
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abdtr: false,
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dwidth: HspiWidth::NONE,
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ddtr: false,
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dummy: DummyCycles::_0,
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}
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}
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}
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/// Error used for HSPI implementation
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum HspiError {
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/// Peripheral configuration is invalid
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InvalidConfiguration,
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/// Operation configuration is invalid
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InvalidCommand,
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/// Size zero buffer passed to instruction
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EmptyBuffer,
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}
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/// HSPI driver.
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pub struct Hspi<'d, T: Instance, M: PeriMode> {
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_peri: PeripheralRef<'d, T>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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d1: Option<PeripheralRef<'d, AnyPin>>,
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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d4: Option<PeripheralRef<'d, AnyPin>>,
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d5: Option<PeripheralRef<'d, AnyPin>>,
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d6: Option<PeripheralRef<'d, AnyPin>>,
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d7: Option<PeripheralRef<'d, AnyPin>>,
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d8: Option<PeripheralRef<'d, AnyPin>>,
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d9: Option<PeripheralRef<'d, AnyPin>>,
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d10: Option<PeripheralRef<'d, AnyPin>>,
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d11: Option<PeripheralRef<'d, AnyPin>>,
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d12: Option<PeripheralRef<'d, AnyPin>>,
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d13: Option<PeripheralRef<'d, AnyPin>>,
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d14: Option<PeripheralRef<'d, AnyPin>>,
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d15: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dqs0: Option<PeripheralRef<'d, AnyPin>>,
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dqs1: Option<PeripheralRef<'d, AnyPin>>,
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dma: Option<ChannelAndRequest<'d>>,
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_phantom: PhantomData<M>,
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config: Config,
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width: HspiWidth,
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}
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impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
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/// Enter memory mode.
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/// The Input `read_config` is used to configure the read operation in memory mode
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pub fn enable_memory_mapped_mode(
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&mut self,
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read_config: TransferConfig,
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write_config: TransferConfig,
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) -> Result<(), HspiError> {
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// Use configure command to set read config
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self.configure_command(&read_config, None)?;
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// Set writing configurations, there are separate registers for write configurations in memory mapped mode
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T::REGS.wccr().modify(|w| {
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w.set_imode(write_config.iwidth.into());
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w.set_idtr(write_config.idtr);
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w.set_isize(write_config.isize.into());
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w.set_admode(write_config.adwidth.into());
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w.set_addtr(write_config.idtr);
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w.set_adsize(write_config.adsize.into());
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w.set_dmode(write_config.dwidth.into());
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w.set_ddtr(write_config.ddtr);
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w.set_abmode(write_config.abwidth.into());
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w.set_dqse(true);
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});
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T::REGS.wtcr().modify(|w| w.set_dcyc(write_config.dummy.into()));
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// Enable memory mapped mode
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T::REGS.cr().modify(|r| {
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r.set_fmode(FunctionalMode::MemoryMapped.into());
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r.set_tcen(false);
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});
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Ok(())
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}
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/// Quit from memory mapped mode
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pub fn disable_memory_mapped_mode(&mut self) {
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T::REGS.cr().modify(|r| {
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r.set_fmode(FunctionalMode::IndirectWrite.into());
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r.set_abort(true);
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r.set_dmaen(false);
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r.set_en(false);
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});
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// Clear transfer complete flag
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T::REGS.fcr().write(|w| w.set_ctcf(true));
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// Re-enable HSPI
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T::REGS.cr().modify(|r| {
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r.set_en(true);
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});
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}
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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d1: Option<PeripheralRef<'d, AnyPin>>,
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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d4: Option<PeripheralRef<'d, AnyPin>>,
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d5: Option<PeripheralRef<'d, AnyPin>>,
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d6: Option<PeripheralRef<'d, AnyPin>>,
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d7: Option<PeripheralRef<'d, AnyPin>>,
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d8: Option<PeripheralRef<'d, AnyPin>>,
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d9: Option<PeripheralRef<'d, AnyPin>>,
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d10: Option<PeripheralRef<'d, AnyPin>>,
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d11: Option<PeripheralRef<'d, AnyPin>>,
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d12: Option<PeripheralRef<'d, AnyPin>>,
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d13: Option<PeripheralRef<'d, AnyPin>>,
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d14: Option<PeripheralRef<'d, AnyPin>>,
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d15: Option<PeripheralRef<'d, AnyPin>>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dqs0: Option<PeripheralRef<'d, AnyPin>>,
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dqs1: Option<PeripheralRef<'d, AnyPin>>,
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dma: Option<ChannelAndRequest<'d>>,
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config: Config,
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width: HspiWidth,
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dual_memory_mode: bool,
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) -> Self {
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into_ref!(peri);
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// System configuration
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rcc::enable_and_reset::<T>();
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// Call this function just to check that the clock for HSPI1 is properly setup
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let _ = T::frequency();
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while T::REGS.sr().read().busy() {}
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Self::configure_registers(&config, Some(dual_memory_mode));
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Self {
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_peri: peri,
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sck,
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d0,
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d1,
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d2,
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d3,
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d4,
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d5,
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d6,
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d7,
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d8,
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d9,
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d10,
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d11,
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d12,
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d13,
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d14,
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d15,
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nss,
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dqs0,
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dqs1,
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dma,
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_phantom: PhantomData,
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config,
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width,
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}
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}
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fn configure_registers(config: &Config, dual_memory_mode: Option<bool>) {
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// Device configuration
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T::REGS.dcr1().modify(|w| {
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w.set_mtyp(config.memory_type.into());
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w.set_devsize(config.device_size.into());
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w.set_csht(config.chip_select_high_time.into());
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w.set_frck(false);
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w.set_ckmode(config.clock_mode);
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w.set_dlybyp(config.delay_block_bypass);
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});
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T::REGS.dcr2().modify(|w| {
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w.set_wrapsize(config.wrap_size.into());
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});
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T::REGS.dcr3().modify(|w| {
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w.set_csbound(config.chip_select_boundary);
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w.set_maxtran(config.max_transfer);
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});
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T::REGS.dcr4().modify(|w| {
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w.set_refresh(config.refresh);
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});
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T::REGS.cr().modify(|w| {
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w.set_fthres(config.fifo_threshold.into());
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});
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// Wait for busy flag to clear
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while T::REGS.sr().read().busy() {}
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T::REGS.dcr2().modify(|w| {
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w.set_prescaler(config.clock_prescaler);
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});
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// The configuration of clock prescaler trigger automatically a calibration process
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// So it is necessary to wait the calibration is complete
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while T::REGS.sr().read().busy() {}
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if let Some(dual_memory_mode) = dual_memory_mode {
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T::REGS.cr().modify(|w| {
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w.set_dmm(dual_memory_mode);
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});
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}
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T::REGS.tcr().modify(|w| {
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w.set_sshift(config.sample_shifting);
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w.set_dhqc(config.delay_hold_quarter_cycle);
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});
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// Enable peripheral
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T::REGS.cr().modify(|w| {
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w.set_en(true);
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});
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// Free running clock needs to be set after peripheral enable
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if config.free_running_clock {
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T::REGS.dcr1().modify(|w| {
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w.set_frck(config.free_running_clock);
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});
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}
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}
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// Function to configure the peripheral for the requested command
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fn configure_command(&mut self, command: &TransferConfig, data_len: Option<usize>) -> Result<(), HspiError> {
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// Check that transaction doesn't use more than hardware initialized pins
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if <enums::HspiWidth as Into<u8>>::into(command.iwidth) > <enums::HspiWidth as Into<u8>>::into(self.width)
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|| <enums::HspiWidth as Into<u8>>::into(command.adwidth) > <enums::HspiWidth as Into<u8>>::into(self.width)
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|| <enums::HspiWidth as Into<u8>>::into(command.abwidth) > <enums::HspiWidth as Into<u8>>::into(self.width)
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|| <enums::HspiWidth as Into<u8>>::into(command.dwidth) > <enums::HspiWidth as Into<u8>>::into(self.width)
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{
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return Err(HspiError::InvalidCommand);
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}
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while T::REGS.sr().read().busy() {}
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T::REGS.cr().modify(|w| {
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w.set_fmode(0.into());
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});
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// Configure alternate bytes
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if let Some(ab) = command.alternate_bytes {
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T::REGS.abr().write(|v| v.set_alternate(ab));
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T::REGS.ccr().modify(|w| {
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w.set_abmode(command.abwidth.into());
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w.set_abdtr(command.abdtr);
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w.set_absize(command.absize.into());
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})
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}
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// Configure dummy cycles
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T::REGS.tcr().modify(|w| {
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w.set_dcyc(command.dummy.into());
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});
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// Configure data
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if let Some(data_length) = data_len {
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T::REGS.dlr().write(|v| {
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v.set_dl((data_length - 1) as u32);
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})
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} else {
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T::REGS.dlr().write(|v| {
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v.set_dl((0) as u32);
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})
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}
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// Configure instruction/address/data modes
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T::REGS.ccr().modify(|w| {
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w.set_imode(command.iwidth.into());
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w.set_idtr(command.idtr);
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w.set_isize(command.isize.into());
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w.set_admode(command.adwidth.into());
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w.set_addtr(command.addtr);
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w.set_adsize(command.adsize.into());
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w.set_dmode(command.dwidth.into());
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w.set_ddtr(command.ddtr);
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});
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// Configure DQS
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T::REGS.ccr().modify(|w| {
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w.set_dqse(command.ddtr && command.instruction.unwrap_or(0) != 0x12ED);
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});
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// Set information required to initiate transaction
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if let Some(instruction) = command.instruction {
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if let Some(address) = command.address {
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T::REGS.ir().write(|v| {
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v.set_instruction(instruction);
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});
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T::REGS.ar().write(|v| {
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v.set_address(address);
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});
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} else {
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T::REGS.ir().write(|v| {
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v.set_instruction(instruction);
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});
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}
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} else {
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if let Some(address) = command.address {
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T::REGS.ar().write(|v| {
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v.set_address(address);
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});
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} else {
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// The only single phase transaction supported is instruction only
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return Err(HspiError::InvalidCommand);
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}
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}
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Ok(())
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}
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/// Function used to control or configure the target device without data transfer
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pub fn blocking_command(&mut self, command: &TransferConfig) -> Result<(), HspiError> {
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// Wait for peripheral to be free
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while T::REGS.sr().read().busy() {}
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// Need additional validation that command configuration doesn't have data set
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self.configure_command(command, None)?;
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// Transaction initiated by setting final configuration, i.e the instruction register
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().write(|w| {
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w.set_ctcf(true);
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});
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Ok(())
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}
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/// Blocking read with byte by byte data transfer
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pub fn blocking_read<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), HspiError> {
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if buf.is_empty() {
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return Err(HspiError::EmptyBuffer);
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}
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// Wait for peripheral to be free
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while T::REGS.sr().read().busy() {}
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// Ensure DMA is not enabled for this transaction
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T::REGS.cr().modify(|w| {
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w.set_dmaen(false);
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});
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self.configure_command(&transaction, Some(buf.len()))?;
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let current_address = T::REGS.ar().read().address();
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let current_instruction = T::REGS.ir().read().instruction();
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|
|
// For a indirect read transaction, the transaction begins when the instruction/address is set
|
|
T::REGS
|
|
.cr()
|
|
.modify(|v| v.set_fmode(FunctionalMode::IndirectRead.into()));
|
|
if T::REGS.ccr().read().admode() == HspiWidth::NONE.into() {
|
|
T::REGS.ir().write(|v| v.set_instruction(current_instruction));
|
|
} else {
|
|
T::REGS.ar().write(|v| v.set_address(current_address));
|
|
}
|
|
|
|
for idx in 0..buf.len() {
|
|
while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
|
|
buf[idx] = unsafe { (T::REGS.dr().as_ptr() as *mut W).read_volatile() };
|
|
}
|
|
|
|
while !T::REGS.sr().read().tcf() {}
|
|
T::REGS.fcr().write(|v| v.set_ctcf(true));
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Blocking write with byte by byte data transfer
|
|
pub fn blocking_write<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), HspiError> {
|
|
if buf.is_empty() {
|
|
return Err(HspiError::EmptyBuffer);
|
|
}
|
|
|
|
// Wait for peripheral to be free
|
|
while T::REGS.sr().read().busy() {}
|
|
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_dmaen(false);
|
|
});
|
|
|
|
self.configure_command(&transaction, Some(buf.len()))?;
|
|
|
|
T::REGS
|
|
.cr()
|
|
.modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into()));
|
|
|
|
for idx in 0..buf.len() {
|
|
while !T::REGS.sr().read().ftf() {}
|
|
unsafe { (T::REGS.dr().as_ptr() as *mut W).write_volatile(buf[idx]) };
|
|
}
|
|
|
|
while !T::REGS.sr().read().tcf() {}
|
|
T::REGS.fcr().write(|v| v.set_ctcf(true));
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Set new bus configuration
|
|
pub fn set_config(&mut self, config: &Config) {
|
|
// Wait for busy flag to clear
|
|
while T::REGS.sr().read().busy() {}
|
|
|
|
// Disable DMA channel while configuring the peripheral
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_dmaen(false);
|
|
});
|
|
|
|
Self::configure_registers(config, None);
|
|
|
|
self.config = *config;
|
|
}
|
|
|
|
/// Get current configuration
|
|
pub fn get_config(&self) -> Config {
|
|
self.config
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> Hspi<'d, T, Blocking> {
|
|
/// Create new blocking HSPI driver for single spi external chip
|
|
pub fn new_blocking_singlespi(
|
|
peri: impl Peripheral<P = T> + 'd,
|
|
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
|
|
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
|
|
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
|
|
nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
|
|
config: Config,
|
|
) -> Self {
|
|
Self::new_inner(
|
|
peri,
|
|
new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d1, AfType::input(Pull::None)),
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(
|
|
nss,
|
|
AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
|
|
),
|
|
None,
|
|
None,
|
|
None,
|
|
config,
|
|
HspiWidth::SING,
|
|
false,
|
|
)
|
|
}
|
|
|
|
/// Create new blocking HSPI driver for octospi external chip
|
|
pub fn new_blocking_octospi(
|
|
peri: impl Peripheral<P = T> + 'd,
|
|
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
|
|
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
|
|
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
|
|
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
|
|
d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
|
|
d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
|
|
d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
|
|
d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
|
|
d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
|
|
nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
|
|
dqs0: impl Peripheral<P = impl DQS0Pin<T>> + 'd,
|
|
config: Config,
|
|
) -> Self {
|
|
Self::new_inner(
|
|
peri,
|
|
new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(
|
|
nss,
|
|
AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
|
|
),
|
|
new_pin!(dqs0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
None,
|
|
None,
|
|
config,
|
|
HspiWidth::OCTO,
|
|
false,
|
|
)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> Hspi<'d, T, Async> {
|
|
/// Create new HSPI driver for a single spi external chip
|
|
pub fn new_singlespi(
|
|
peri: impl Peripheral<P = T> + 'd,
|
|
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
|
|
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
|
|
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
|
|
nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
|
|
dma: impl Peripheral<P = impl HspiDma<T>> + 'd,
|
|
config: Config,
|
|
) -> Self {
|
|
Self::new_inner(
|
|
peri,
|
|
new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d1, AfType::input(Pull::None)),
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(
|
|
nss,
|
|
AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
|
|
),
|
|
None,
|
|
None,
|
|
new_dma!(dma),
|
|
config,
|
|
HspiWidth::SING,
|
|
false,
|
|
)
|
|
}
|
|
|
|
/// Create new HSPI driver for octospi external chip
|
|
pub fn new_octospi(
|
|
peri: impl Peripheral<P = T> + 'd,
|
|
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
|
|
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
|
|
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
|
|
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
|
|
d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
|
|
d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
|
|
d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
|
|
d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
|
|
d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
|
|
nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
|
|
dqs0: impl Peripheral<P = impl DQS0Pin<T>> + 'd,
|
|
dma: impl Peripheral<P = impl HspiDma<T>> + 'd,
|
|
config: Config,
|
|
) -> Self {
|
|
Self::new_inner(
|
|
peri,
|
|
new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
None,
|
|
new_pin!(
|
|
nss,
|
|
AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
|
|
),
|
|
new_pin!(dqs0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
|
|
None,
|
|
new_dma!(dma),
|
|
config,
|
|
HspiWidth::OCTO,
|
|
false,
|
|
)
|
|
}
|
|
|
|
/// Blocking read with DMA transfer
|
|
pub fn blocking_read_dma<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), HspiError> {
|
|
if buf.is_empty() {
|
|
return Err(HspiError::EmptyBuffer);
|
|
}
|
|
|
|
// Wait for peripheral to be free
|
|
while T::REGS.sr().read().busy() {}
|
|
|
|
self.configure_command(&transaction, Some(buf.len()))?;
|
|
|
|
let current_address = T::REGS.ar().read().address();
|
|
let current_instruction = T::REGS.ir().read().instruction();
|
|
|
|
// For a indirect read transaction, the transaction begins when the instruction/address is set
|
|
T::REGS
|
|
.cr()
|
|
.modify(|v| v.set_fmode(FunctionalMode::IndirectRead.into()));
|
|
if T::REGS.ccr().read().admode() == HspiWidth::NONE.into() {
|
|
T::REGS.ir().write(|v| v.set_instruction(current_instruction));
|
|
} else {
|
|
T::REGS.ar().write(|v| v.set_address(current_address));
|
|
}
|
|
|
|
let transfer = unsafe {
|
|
self.dma
|
|
.as_mut()
|
|
.unwrap()
|
|
.read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
|
|
};
|
|
|
|
T::REGS.cr().modify(|w| w.set_dmaen(true));
|
|
|
|
transfer.blocking_wait();
|
|
|
|
finish_dma(T::REGS);
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Blocking write with DMA transfer
|
|
pub fn blocking_write_dma<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), HspiError> {
|
|
if buf.is_empty() {
|
|
return Err(HspiError::EmptyBuffer);
|
|
}
|
|
|
|
// Wait for peripheral to be free
|
|
while T::REGS.sr().read().busy() {}
|
|
|
|
self.configure_command(&transaction, Some(buf.len()))?;
|
|
T::REGS
|
|
.cr()
|
|
.modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into()));
|
|
|
|
let transfer = unsafe {
|
|
self.dma
|
|
.as_mut()
|
|
.unwrap()
|
|
.write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
|
|
};
|
|
|
|
T::REGS.cr().modify(|w| w.set_dmaen(true));
|
|
|
|
transfer.blocking_wait();
|
|
|
|
finish_dma(T::REGS);
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Asynchronous read from external device
|
|
pub async fn read<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), HspiError> {
|
|
if buf.is_empty() {
|
|
return Err(HspiError::EmptyBuffer);
|
|
}
|
|
|
|
// Wait for peripheral to be free
|
|
while T::REGS.sr().read().busy() {}
|
|
|
|
self.configure_command(&transaction, Some(buf.len()))?;
|
|
|
|
let current_address = T::REGS.ar().read().address();
|
|
let current_instruction = T::REGS.ir().read().instruction();
|
|
|
|
// For a indirect read transaction, the transaction begins when the instruction/address is set
|
|
T::REGS
|
|
.cr()
|
|
.modify(|v| v.set_fmode(FunctionalMode::IndirectRead.into()));
|
|
if T::REGS.ccr().read().admode() == HspiWidth::NONE.into() {
|
|
T::REGS.ir().write(|v| v.set_instruction(current_instruction));
|
|
} else {
|
|
T::REGS.ar().write(|v| v.set_address(current_address));
|
|
}
|
|
|
|
let transfer = unsafe {
|
|
self.dma
|
|
.as_mut()
|
|
.unwrap()
|
|
.read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
|
|
};
|
|
|
|
T::REGS.cr().modify(|w| w.set_dmaen(true));
|
|
|
|
transfer.await;
|
|
|
|
finish_dma(T::REGS);
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Asynchronous write to external device
|
|
pub async fn write<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), HspiError> {
|
|
if buf.is_empty() {
|
|
return Err(HspiError::EmptyBuffer);
|
|
}
|
|
|
|
// Wait for peripheral to be free
|
|
while T::REGS.sr().read().busy() {}
|
|
|
|
self.configure_command(&transaction, Some(buf.len()))?;
|
|
T::REGS
|
|
.cr()
|
|
.modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into()));
|
|
|
|
let transfer = unsafe {
|
|
self.dma
|
|
.as_mut()
|
|
.unwrap()
|
|
.write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
|
|
};
|
|
|
|
T::REGS.cr().modify(|w| w.set_dmaen(true));
|
|
|
|
transfer.await;
|
|
|
|
finish_dma(T::REGS);
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: PeriMode> Drop for Hspi<'d, T, M> {
|
|
fn drop(&mut self) {
|
|
self.sck.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d0.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d1.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d2.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d3.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d4.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d5.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d6.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d7.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d8.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d9.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d10.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d11.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d12.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d13.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d14.as_ref().map(|x| x.set_as_disconnected());
|
|
self.d15.as_ref().map(|x| x.set_as_disconnected());
|
|
self.nss.as_ref().map(|x| x.set_as_disconnected());
|
|
self.dqs0.as_ref().map(|x| x.set_as_disconnected());
|
|
self.dqs1.as_ref().map(|x| x.set_as_disconnected());
|
|
|
|
rcc::disable::<T>();
|
|
}
|
|
}
|
|
|
|
fn finish_dma(regs: Regs) {
|
|
while !regs.sr().read().tcf() {}
|
|
regs.fcr().write(|v| v.set_ctcf(true));
|
|
|
|
regs.cr().modify(|w| {
|
|
w.set_dmaen(false);
|
|
});
|
|
}
|
|
|
|
/// HSPI instance trait.
|
|
pub(crate) trait SealedInstance {
|
|
const REGS: Regs;
|
|
}
|
|
|
|
/// HSPI instance trait.
|
|
#[allow(private_bounds)]
|
|
pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
|
|
|
|
pin_trait!(SckPin, Instance);
|
|
pin_trait!(NckPin, Instance);
|
|
pin_trait!(D0Pin, Instance);
|
|
pin_trait!(D1Pin, Instance);
|
|
pin_trait!(D2Pin, Instance);
|
|
pin_trait!(D3Pin, Instance);
|
|
pin_trait!(D4Pin, Instance);
|
|
pin_trait!(D5Pin, Instance);
|
|
pin_trait!(D6Pin, Instance);
|
|
pin_trait!(D7Pin, Instance);
|
|
pin_trait!(D8Pin, Instance);
|
|
pin_trait!(D9Pin, Instance);
|
|
pin_trait!(D10Pin, Instance);
|
|
pin_trait!(D11Pin, Instance);
|
|
pin_trait!(D12Pin, Instance);
|
|
pin_trait!(D13Pin, Instance);
|
|
pin_trait!(D14Pin, Instance);
|
|
pin_trait!(D15Pin, Instance);
|
|
pin_trait!(DQS0Pin, Instance);
|
|
pin_trait!(DQS1Pin, Instance);
|
|
pin_trait!(NSSPin, Instance);
|
|
dma_trait!(HspiDma, Instance);
|
|
|
|
foreach_peripheral!(
|
|
(hspi, $inst:ident) => {
|
|
impl SealedInstance for peripherals::$inst {
|
|
const REGS: Regs = crate::pac::$inst;
|
|
}
|
|
|
|
impl Instance for peripherals::$inst {}
|
|
};
|
|
);
|
|
|
|
impl<'d, T: Instance, M: PeriMode> SetConfig for Hspi<'d, T, M> {
|
|
type Config = Config;
|
|
type ConfigError = ();
|
|
fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
|
|
self.set_config(config);
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: PeriMode> GetConfig for Hspi<'d, T, M> {
|
|
type Config = Config;
|
|
fn get_config(&self) -> Self::Config {
|
|
self.get_config()
|
|
}
|
|
}
|
|
|
|
/// Word sizes usable for HSPI.
|
|
#[allow(private_bounds)]
|
|
pub trait Word: word::Word {}
|
|
|
|
macro_rules! impl_word {
|
|
($T:ty) => {
|
|
impl Word for $T {}
|
|
};
|
|
}
|
|
|
|
impl_word!(u8);
|
|
impl_word!(u16);
|
|
impl_word!(u32);
|