107 lines
2.5 KiB
Rust
107 lines
2.5 KiB
Rust
#[allow(dead_code)]
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#[derive(Clone, Copy)]
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pub enum Register {
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ECON1 = 0x1f,
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ECON2 = 0x1e,
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EIE = 0x1b,
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EIR = 0x1c,
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ESTAT = 0x1d,
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}
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impl Register {
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pub(crate) fn addr(&self) -> u8 {
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*self as u8
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}
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pub(crate) fn is_eth_register(&self) -> bool {
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match *self {
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Register::ECON1 => true,
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Register::ECON2 => true,
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Register::EIE => true,
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Register::EIR => true,
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Register::ESTAT => true,
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}
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}
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}
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impl Into<super::Register> for Register {
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fn into(self) -> super::Register {
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super::Register::Common(self)
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}
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}
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register!(EIE, 0, u8, {
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#[doc = "Receive Error Interrupt Enable bit"]
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rxerie @ 0,
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#[doc = "Transmit Error Interrupt Enable bit"]
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txerie @ 1,
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#[doc = "Transmit Enable bit"]
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txie @ 3,
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#[doc = "Link Status Change Interrupt Enable bit"]
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linkie @ 4,
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#[doc = "DMA Interrupt Enable bit"]
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dmaie @ 5,
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#[doc = "Receive Packet Pending Interrupt Enable bit"]
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pktie @ 6,
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#[doc = "Global INT Interrupt Enable bit"]
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intie @ 7,
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});
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register!(EIR, 0, u8, {
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#[doc = "Receive Error Interrupt Flag bit"]
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rxerif @ 0,
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#[doc = "Transmit Error Interrupt Flag bit"]
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txerif @ 1,
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#[doc = "Transmit Interrupt Flag bit"]
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txif @ 3,
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#[doc = "Link Change Interrupt Flag bit"]
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linkif @ 4,
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#[doc = "DMA Interrupt Flag bit"]
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dmaif @ 5,
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#[doc = "Receive Packet Pending Interrupt Flag bit"]
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pktif @ 6,
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});
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register!(ESTAT, 0, u8, {
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#[doc = "Clock Ready bit"]
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clkrdy @ 0,
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#[doc = "Transmit Abort Error bit"]
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txabrt @ 1,
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#[doc = "Receive Busy bit"]
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rxbusy @ 2,
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#[doc = "Late Collision Error bit"]
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latecol @ 4,
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#[doc = "Ethernet Buffer Error Status bit"]
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bufer @ 6,
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#[doc = "INT Interrupt Flag bit"]
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int @ 7,
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});
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register!(ECON2, 0b1000_0000, u8, {
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#[doc = "Voltage Regulator Power Save Enable bit"]
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vrps @ 3,
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#[doc = "Power Save Enable bit"]
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pwrsv @ 5,
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#[doc = "Packet Decrement bit"]
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pktdec @ 6,
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#[doc = "Automatic Buffer Pointer Increment Enable bit"]
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autoinc @ 7,
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});
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register!(ECON1, 0, u8, {
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#[doc = "Bank Select bits"]
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bsel @ 0..1,
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#[doc = "Receive Enable bi"]
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rxen @ 2,
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#[doc = "Transmit Request to Send bit"]
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txrts @ 3,
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#[doc = "DMA Checksum Enable bit"]
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csumen @ 4,
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#[doc = "DMA Start and Busy Status bit"]
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dmast @ 5,
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#[doc = "Receive Logic Reset bit"]
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rxrst @ 6,
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#[doc = "Transmit Logic Reset bit"]
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txrst @ 7,
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});
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